How to configure the CPOL and CPHA values in AXI SPI IP block and SDK? (device as master)

[jg_spitfire]

Hi, I am working in a SPI communication with a zynq FPGA as the master, I am using the SPI IP block (standard SPI) and sending the data from the zynq 's ARM, in the examples provided by xilinx for the slave I can read this:

	/*
	 * The SPI device is a slave by default and the clock phase
	 * have to be set according to its master. In this example, CPOL is set
	 * to quiescent high and CPHA is set to 1.
	 */
	Status = XSpiPs_SetOptions((&SpiInstance), (XSPIPS_CR_CPHA_MASK) | \
			(XSPIPS_CR_CPOL_MASK));
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

but in the example for the master SPI they never mention the CPOL or CPHA in the config:

	/*
	 * Set the Spi device as a master
	 */
	Status = XSpi_SetOptions(SpiInstancePtr, XSP_MASTER_OPTION |
			XSP_MANUAL_SSELECT_OPTION);  						
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

and in vivado block diagram I cant find either the way to change this options

how could I set this options?

thanks