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Registered: ‎01-07-2015

How to connect ADC FMC Card to Zedboard?

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Hi,

 

I'm a beginner (just finnished the AVNET Speedway tutrials) and I want to connect the AD7961 ADC's FMC board (EVAL-AD7961-FMCZ) to the Zedboard. There is no example that shows the use of FMC in the Speedway tutorials as well. Anyway I already have a verilog driver for the AD7961 from an example from Analog Devices intended for the Microblazed based design on KC705 board (file attached). The driver module has the following interface:

 

module AD7961
(
input m_clk_i, // 100 MHz Clock, used for tiing
input fast_clk_i, // Maximum 300 MHz Clock, used for serial transfer
input reset_n_i, // Reset signal, active low
input [ 3:0] en_i, // Enable pins input
input d_pos_i, // Data In, Positive Pair
input d_neg_i, // Data In, Negative Pair
input dco_pos_i, // Echoed Clock In, Positive Pair
input dco_neg_i, // Echoed Clock In, Negative Pair
output [ 3:0] en_o, // Enable pins output
output cnv_pos_o, // Convert Out, Positive Pair
output cnv_neg_o, // Convert Out, Negative Pair
output clk_pos_o, // Clock Out, Positive Pair
output clk_neg_o, // Clock Out, Negative Pair
output data_rd_rdy_o, // Signals that new data is available
output [15:0] data_o // Read Data
);

 

I want to use the ADC in echoed clock mode. I want to get the data from the ADC to the PS and then do some operations in there. Could you please help me with how should I proceed? What would be the main steps I should perform?

 

Thanks.

 

Regards,

 

Shan

 

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Teacher
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Registered: ‎03-31-2012
Yes, so far it looks OK except the clocks. I am not sure the internal connectivity in adc module so I am not sure why you need two clocks. Also there is a clock going to the FMC and coming from FMC. One of these should be generated from the PS clocks. I just noticed that your ADC is a 5 MHz one so you might even be able to do the strobe based transfer. PS/PL interface with one of the GP AXI ports can handle upto 20 MB/s so if you stored two samples of the ADC output, you can poll on a bit from the axi lite slave and read one word or use an interrupt. At this rate you probably don't need DMA.
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Teacher
Teacher
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Registered: ‎03-31-2012
This adc module defines what your interface is to the adc chip sitting on the FMC module. You need to do the following steps:
* add a top level module which receives the output from ad7961 modules and stores it in say BRAM.
* make an axi slave which includes this top level module so that PS side can read the BRAMs.
* connect your axi slave to the PS in a block diagram to generate your fpga design
* add the FMC constraints of your board into an XDC file.
* implement the FPGA design and get a bit file.
* write a piece of code to run on the arm processor in PS to use the axi slave to retrieve the captured data.

This is a rough list. There are steps which are missing but it would point you in the direction you need to go.
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Registered: ‎01-07-2015

Thanks Muzaffer. I decided to make a AXI4Lite based custom IP for this adc driver and connect it to PS. I intend to read the ADC output from the PS. 

 

Could you please see the block diagram and see if this is correct.

 

  1. Also the ADC output data is available when the ADC ouput pin data_rd_rdy_o goes high. How do I read data through AXI only when data is available?
  2. Also could you please help me out with the clocks. I generated two clocks from PS (100MHz and 250MHz) and then assigned the 250MHz clock to s00_axi_aclk (because it says "clock for serial transfer" in the driver definition)and the 100MHz to the port m_clk_in. Do you think this is correct?
  3. I converted all the signals that need to connect to the FMC to external(with net names from XDC) but I cannot assign FMC net names from XDC to each individual line of the 4-bit en_out[3:0] (highlighted in yellow) .How can I do that?

Thank you Muzaffer. I really appreciate your help. Your previous replies (another post) also helped me alot.

 

Regards,

 

Zeeshan

 

Capture3.PNG

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Teacher
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Registered: ‎03-31-2012

I decided to make a AXI4Lite based custom IP for this adc driver and connect it to PS. I intend to read the ADC output from the PS. 

 

This is probably not a good idea. PS can't keep up with the rate of the data coming from the ADC. You should create a capture interface which includes a start / length information and a PL module which implements this interface. Ie when start is signalled PL captures length amount of data into a BRAM. Then PS can read this data at its convenience.

If you need to capture & process continously, it's probably a good idea to either do it in PL as you have more control on timing or implement some form of DMA to PS memory.

 

I converted all the signals that need to connect to the FMC to external(with net names from XDC) but I cannot assign FMC net names from XDC to each individual line of the 4-bit en_out[3:0] (highlighted in yellow) .How can I do that?

 

You can use the slice IP to split that vector.

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Registered: ‎01-07-2015

Thank you Muzaffer. You are right, I may run into problem later on if I do this. But is this design correct uptil making the custom IP? All I need is to use a DMA now? So anyway I will try to incorporate a DMA in the design and request help when I'm stuck. Thank you again.

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Teacher
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Registered: ‎03-31-2012
Yes, so far it looks OK except the clocks. I am not sure the internal connectivity in adc module so I am not sure why you need two clocks. Also there is a clock going to the FMC and coming from FMC. One of these should be generated from the PS clocks. I just noticed that your ADC is a 5 MHz one so you might even be able to do the strobe based transfer. PS/PL interface with one of the GP AXI ports can handle upto 20 MB/s so if you stored two samples of the ADC output, you can poll on a bit from the axi lite slave and read one word or use an interrupt. At this rate you probably don't need DMA.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post