01-18-2015 11:38 PM
I'm a beginner (just finnished the AVNET Speedway tutrials) and I want to connect the AD7961 ADC's FMC board (EVAL-AD7961-FMCZ) to the Zedboard. There is no example that shows the use of FMC in the Speedway tutorials as well. Anyway I already have a verilog driver for the AD7961 from an example from Analog Devices intended for the Microblazed based design on KC705 board (file attached). The driver module has the following interface:
input m_clk_i, // 100 MHz Clock, used for tiing
input fast_clk_i, // Maximum 300 MHz Clock, used for serial transfer
input reset_n_i, // Reset signal, active low
input [ 3:0] en_i, // Enable pins input
input d_pos_i, // Data In, Positive Pair
input d_neg_i, // Data In, Negative Pair
input dco_pos_i, // Echoed Clock In, Positive Pair
input dco_neg_i, // Echoed Clock In, Negative Pair
output [ 3:0] en_o, // Enable pins output
output cnv_pos_o, // Convert Out, Positive Pair
output cnv_neg_o, // Convert Out, Negative Pair
output clk_pos_o, // Clock Out, Positive Pair
output clk_neg_o, // Clock Out, Negative Pair
output data_rd_rdy_o, // Signals that new data is available
output [15:0] data_o // Read Data
I want to use the ADC in echoed clock mode. I want to get the data from the ADC to the PS and then do some operations in there. Could you please help me with how should I proceed? What would be the main steps I should perform?
01-20-2015 12:51 AM
01-19-2015 11:16 PM
01-19-2015 11:58 PM
Thanks Muzaffer. I decided to make a AXI4Lite based custom IP for this adc driver and connect it to PS. I intend to read the ADC output from the PS.
Could you please see the block diagram and see if this is correct.
Thank you Muzaffer. I really appreciate your help. Your previous replies (another post) also helped me alot.
01-20-2015 12:09 AM - edited 01-20-2015 12:12 AM
I decided to make a AXI4Lite based custom IP for this adc driver and connect it to PS. I intend to read the ADC output from the PS.
This is probably not a good idea. PS can't keep up with the rate of the data coming from the ADC. You should create a capture interface which includes a start / length information and a PL module which implements this interface. Ie when start is signalled PL captures length amount of data into a BRAM. Then PS can read this data at its convenience.
If you need to capture & process continously, it's probably a good idea to either do it in PL as you have more control on timing or implement some form of DMA to PS memory.
I converted all the signals that need to connect to the FMC to external(with net names from XDC) but I cannot assign FMC net names from XDC to each individual line of the 4-bit en_out[3:0] (highlighted in yellow) .How can I do that?
You can use the slice IP to split that vector.
01-20-2015 12:38 AM
Thank you Muzaffer. You are right, I may run into problem later on if I do this. But is this design correct uptil making the custom IP? All I need is to use a DMA now? So anyway I will try to incorporate a DMA in the design and request help when I'm stuck. Thank you again.
01-20-2015 12:51 AM