10-20-2020 03:05 AM
Hi everyone,
I am trying to simulate I2C communication. I have instantiated I2C master and I2C slave in a top module. The sda and scl lines of both the instances should be bidirectional i.e., inout.
Because straight forward connecting of inout ports results in error on synthesis, using Xilinx ISE
"ERROR:Xst:528 - Multi-source in Unit <XXXX> on signal <sda_M_SIG>; this signal is connected to multiple drivers.",
I am trying to use an enable signal to implement tristate buffers after referring to some forum posts. The code is as follows.
architecture mixed of I2C is
signal scl: std_logic;
signal sda_M_SIG: std_logic;
signal sda_S_SIG: std_logic;
signal sda_ena_SIG: std_logic;
signal sda_ena_n_SIG: std_logic;
component i2c_master
port(
sda : inout std_logic;
scl : inout std_logic;
sda_ena : out std_logic
);
end component;
component i2c_slave
port(
scl: inout;
sda: inout
);
end component;
begin
sda_ena_n_SIG <= not sda_ena_SIG;
sda_S_SIG <= sda_M_SIG when(sda_ena_SIG='1') else 'Z';
sda_M_SIG <= sda_S_SIG when(sda_ena_n_SIG='1') else 'Z';
Inst_I2C_master: i2c_master
port map(
scl => scl,
sda => sda_M_SIG,
sda_ena => sda_ena_SIG
);
Inst_I2C_slave: i2c_slave
port map(
scl => scl,
sda => sda_S_SIG
);
end mixed;
However I still get the same error on synthesis, using Xilinx ISE "ERROR:Xst:528 - Multi-source in Unit <XXXX> on signal <sda_M_SIG>; this signal is connected to multiple drivers."
Can someone suggest how I can connect the sda and scl ports of the components I2C master and slave?
Thanks in advance,
-Chandrasekhar DVS
10-20-2020 04:04 PM
If you are going to implement I2C with an FPGA then eventually you will need to use IOBUF.
So, as you write and simulate your components, it is a good idea to prepare for the use of IOBUF. For example, your i2c_master component will need to look like the following:
component i2c_master
port(
sda_i : in std_logic;
sda_o : out std_logic;
sda_en : out std_logic
scl_i : in std_logic;
scl_o : out std_logic;
scl_en : out std_logic
);
end component;
Then, at the top-level of your design, ports of i2c_master connect to an IOBUF as follows:
-and similarly for scl_i, scl_o, and scl_en to a separate IOBUF.
For more information on using the FPGA to do I2C, see the following post.
https://forums.xilinx.com/t5/Other-FPGA-Architecture/i2c-signal-bypass-fpga/m-p/855773
Cheers,
Mark
10-20-2020 05:12 AM
10-20-2020 09:26 AM
Hi @drjohnsmith ,
As you said, I am only attempting simulation. We would later be getting a hardware that would serve as i2c slave. Before the piece of hardware arrives, I wanted to be sure if the i2c master is working properly and wanted to look at the i2c slave acknowledgement. Hence I got hold of a vhdl code that I could use in my top module and hence the attempt.
However I don't think I can simulate without synthesising it? I don't know. I am using Xilinx ISE 13.2 by the way for this. Can you provide some insight here?
Also you were talking about me having access to the IP I am using? I did not get the point. Could you please elaborate?
Thanks in advance,
-Chandrasekhar DVS
10-20-2020 10:30 AM
You can perform a behavioral simulation without synthesizing.
10-20-2020 11:02 AM
10-20-2020 04:04 PM
If you are going to implement I2C with an FPGA then eventually you will need to use IOBUF.
So, as you write and simulate your components, it is a good idea to prepare for the use of IOBUF. For example, your i2c_master component will need to look like the following:
component i2c_master
port(
sda_i : in std_logic;
sda_o : out std_logic;
sda_en : out std_logic
scl_i : in std_logic;
scl_o : out std_logic;
scl_en : out std_logic
);
end component;
Then, at the top-level of your design, ports of i2c_master connect to an IOBUF as follows:
-and similarly for scl_i, scl_o, and scl_en to a separate IOBUF.
For more information on using the FPGA to do I2C, see the following post.
https://forums.xilinx.com/t5/Other-FPGA-Architecture/i2c-signal-bypass-fpga/m-p/855773
Cheers,
Mark
10-26-2020 09:13 PM