How to connect sda and scl lines of I2c master and i2c slave?

[krishnachandrasekhar100]

Hi everyone,

I am trying to simulate I2C communication. I have instantiated I2C master and I2C slave in a top module. The sda and scl lines of both the instances should be bidirectional i.e., inout.

Because straight forward connecting of inout ports results in error on synthesis, using Xilinx ISE

"ERROR:Xst:528 - Multi-source in Unit <XXXX> on signal <sda_M_SIG>; this signal is connected to multiple drivers.",

I am trying to use an enable signal to implement tristate buffers after referring to some forum posts. The code is as follows.

architecture mixed of I2C is

signal scl: std_logic;

signal sda_M_SIG: std_logic;

signal sda_S_SIG: std_logic;

signal sda_ena_SIG: std_logic;

signal sda_ena_n_SIG: std_logic;

component i2c_master

port(

  sda : inout std_logic;

  scl : inout std_logic;

  sda_ena : out std_logic

);

end component;

component i2c_slave

port(

  scl: inout;

  sda: inout

);

end component;

begin

sda_ena_n_SIG <= not sda_ena_SIG;

sda_S_SIG <= sda_M_SIG when(sda_ena_SIG='1') else 'Z';

sda_M_SIG <= sda_S_SIG when(sda_ena_n_SIG='1') else 'Z';

Inst_I2C_master: i2c_master

port map(

 scl => scl,

 sda => sda_M_SIG,

 sda_ena => sda_ena_SIG

);

Inst_I2C_slave: i2c_slave

port map(

 scl => scl,

 sda => sda_S_SIG

);

end mixed;

However I still get the same error on synthesis, using Xilinx ISE  "ERROR:Xst:528 - Multi-source in Unit <XXXX> on signal <sda_M_SIG>; this signal is connected to multiple drivers."

Can someone suggest how I can connect the sda and scl ports of the components I2C master and slave?

Thanks in advance,

-Chandrasekhar DVS

[drjohnsmith]

i2C uses bi directional , open collector signals,
No FPAG can not support open collector bi directional signals inside the chip.
( I think the very old spartan of the 1990's could , but that's well EOL )

I2C can be simulated,
you need to ensure you have a "H" driver on the lines, and Xto01 on any input , but it can not be synthesised into a chip

if you want an internal serial bus,

use SPI , which is all un i direction and 0/1 levels,

or if you have access to the IP your using, then inside the IP will be the single ended , unidirectional signals, before they get muxed on to bi directional OC lines. They can be routed inside the FPAG.

[krishnachandrasekhar100]

Hi @drjohnsmith ,

As you said, I am only attempting simulation. We would later be getting a hardware that would serve as i2c slave. Before the piece of hardware arrives, I wanted to be sure if the i2c master is working properly and wanted to look at the i2c slave acknowledgement. Hence I got hold of a vhdl code that I could use in my top module and hence the attempt.

However I don't think I can simulate without synthesising it? I don't know. I am using Xilinx ISE 13.2 by the way for this. Can you provide some insight here?

Also you were talking about me having access to the IP I am using? I did not get the point. Could you please elaborate?

Thanks in advance,

-Chandrasekhar DVS

[bruce_karaffa]

You can perform a behavioral simulation without synthesizing. 

[drjohnsmith]

Hi,
so as bruce jumped in and said,
synthesis and simulation are different,

Synthesis takes your design and tries to make it into an FPGA
simulation takes your code, and emulates what it does,
the difference is significant,
for instance in simulation you can have tri state and open collector signals, which are great for outside of the FPGA, but can not be inside the FPGA.

remember, for I2C simulation, you are going to have to add the simulation for the i2C pull ups , done with the H signal in VHDL, and your receivers are going to have to have have xto01, to take account of the H and Tristate they are going to see.

[markg@prosensing.com · Accepted solution]

@krishnachandrasekhar100 

If you are going to implement I2C with an FPGA then eventually you will need to use IOBUF.

So, as you write and simulate your components, it is a good idea to prepare for the use of IOBUF.  For example, your i2c_master component will need to look like the following:

component i2c_master
port(
  sda_i : in std_logic;
  sda_o : out std_logic;
  sda_en : out std_logic
  scl_i : in std_logic;
  scl_o : out std_logic;
  scl_en : out std_logic
);
end component;

Then, at the top-level of your design, ports of i2c_master connect to an IOBUF as follows:

• sda_i connects to O-pin of IOBUF
• sda_o connects to I-pin of IOBUF
• sda_en connecs to T-pin of IOBUF

-and similarly for scl_i, scl_o, and scl_en to a separate IOBUF.

For more information on using the FPGA to do I2C, see the following post.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/i2c-signal-bypass-fpga/m-p/855773

Cheers,
Mark

[krishnachandrasekhar100]

Hi markg@prosensing.com ,

Thanks! That helped!

-Chandrasekhar DVS