05-03-2015 04:00 AM
I've got a Zynq 7000 design, in which memory mapped AXI slaves are connected to the PS via GP0 and GP1.
The PS initiates read and write transactions to write into and read from the slaves with the arbitrarily chosen IDs (please correct me if I'm wrong).
This cause the system to hang, because the AXI slaves can not deliver the responses to the PS.
The problem is that the slaves connected to the PS have the limitted ID range (i.e., 6 bit from 0x00 to 0x1F) while the PS in case the static ID remapping is enabled, initiates transactions with IDs from 0x00 through 0xFF (as far as I could find out by iLA of Vivado).
My question is wether there is a possibility that I can limit the generated IDs by the PS (e.g., 0x00 to 0x1F)?
If not, is there any IP core within the Vivado by which I can decouple the transactions and bound the transaction IDs at the master side of that IP?
05-03-2015 07:57 PM
05-04-2015 01:08 AM
I don't understand why the IDs seen by the slaves are 13 bits, while the generated IDs by GP0/1 are either 12 or 6 bits (in case of static ID remapping).
For instance, how these IDs change when the static remapping is enabled?
If so, why should we maintain the IDs generated by the CPU up to the slave within the PL?