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shairva
Explorer
Explorer
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Registered: ‎09-19-2018

How to debug an AXI4 peripheral ?

Hi, I have created an AXI4 peripheral using: Tools -> Create and package new IP -> Create AXI4 Peripheral

image

The pic above is my design. So, I'm using DEVMEM command (in Petalinux) to send data from the PS to the PL. The data sent should go through those 3 outputs in orange, and I would like to get that data through the ILA or something like that.

Is that possible? 

Thanks in advance. 

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@shairva ,

There are several avenues available to you for debugging custom AXI peripherals.

  • The first thing you need to know is that Xilinx's AXI demonstration peripherals are broken.  Both the AXI4 slave and AXI4-lite slave have been broken since 2016 if not before.  They are still broken as of Vivado 2020.2.  They will hang your system.  It's just a matter of time until they do.  (Check out ZipCPU's blog for more information on both the bugs and the fixes)
  • My favorite / recommended debugging method is to formally verify any AXI designs to make certain the interface works as desired.  This will find bugs that nothing else will, and for 5-10 minutes of debugging will spare you the hassle of being up every night for a week wondering why your circuit board suddenly stops working.
  • If your design passes a formal verification check, then check out Xilinx's AXI VIP suite.  That should allow you to simulate your design and see whether it responds properly in simulation.  (Beware, Xilinx's VIP suite will mask bugs that the formal check will find--so skipping to this step doesn't really help you.)
  • Only after formal and simulation should you then move to debugging in hardware.  In that case, yes, you can (and probably should) use the ILA to find out what's going on.  I might argue, though, that if a bug gets past the prior steps then you have a problem in your process.  This is the hard and painful way to debug--it takes a lot of time.  Don't let yourself get stuck in this position.  Catch the bugs first with formal and simulation!

Dan

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