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Visitor
Visitor
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Registered: ‎11-03-2012

How to design a module with axis slave input to axis master output?

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This may be a very simple and common question, but it makes me confused for a long time.

Here is what I want to design. The module receives data from axis slave port and after processing, sends out the result through axis master port. Let me make it simpler:

 

input    s_axis_tvalid,

output  s_axis_tready,

input    s_axis_tdata,

output  m_axis_tvalid,

input    m_axis_tready,

output  m_axis_tdata

 

reg   data_pipe1, data_pipe2, data_pipe3;

assign  m_axis_tdata  = data_pipe3; 

... ...

 

It means that, the output data has 3 clock cycle latency compared to the input data. My question is, how to deal with the ready & valid handshake (on both slave and master side) in this module? Thanks!

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Teacher
Teacher
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Registered: ‎03-31-2012

@wudpeker what you need is a fifo at the output of the data pipeline to completely isolate the two sides. You have to make sure that the slave at the output has enough bandwidth to drain the fifo but that's all you need. Everything else will just work. 

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Teacher
Teacher
7,347 Views
Registered: ‎03-31-2012

@wudpeker what you need is a fifo at the output of the data pipeline to completely isolate the two sides. You have to make sure that the slave at the output has enough bandwidth to drain the fifo but that's all you need. Everything else will just work. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Visitor
Visitor
3,905 Views
Registered: ‎11-03-2012

@muzaffer Thanks. I am doing it as you suggested. But I am curious to ask, is there any other way except FIFO?

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Teacher
Teacher
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Registered: ‎03-31-2012

@wudpeker you can implement a set complicated state machines which can manage both receive and transmit channels and use minimal storage but I think that's not worth the complication. A simple receive & buffer slave, process datapath and transmit master pipeline works well, gives an easy to maintain design and in the end is much more efficient as designing, debugging and maintaining such a block is the highest cost.

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Visitor
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Registered: ‎11-03-2012

@muzaffer ,I can't agree with you more. But furthermore, I have one more question. I noticed that Vivado supplies AXIS register slice ip, which is something like the AXIS decoupler. When do we need this kind of ip? Since there is no need to implement a "decoupler" if we use FIFO in our design. Thanks!

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Teacher
Teacher
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Registered: ‎03-31-2012

@wudpeker the axi register slice blocks are for timing optimization and extremely useful for fixing timing violations when you don't have control of the ip. They allow transparently adding pipeline stages to the connectivity and allow timing to pass when source & destination are too far away. They are very useful at the boundaries of different blocks.

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Visitor
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Registered: ‎11-03-2012
@muzaffer, got it! Thanks, it really helps a lot.
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