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Visitor
Visitor
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Registered: ‎07-12-2018

How to design and run Microblaze dual core (Realtime variant) in lockstep configuration

I would like to design a dual core (R-variant) micorblaze core to reun in lock step mode.

When I desgined and ran a simple application, the micorblaze_o seems to be running but microblaze_1 seems show error (no clock).

 

Any idea?

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-01-2014


Are you using TMR Microblaze in lock-step configuration? Examples design is provided the IP, it doesn’t work?
http://www.xilinx.com/support/documentation/ip_documentation/tmr/v1_0/pg268-tmr.pdf
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Visitor
Visitor
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Registered: ‎07-12-2018

Yes. I tried TMR. I also read the data sheet.

As per the HDF file the TRM manager base address is 0x44A10000.

As per the data sheet, I tried to inject fault using the register address 0x44A1002C (mwr 0x44a1002c 0x1). As per the document, the 0x44A10004 shall be updated with a non zero value.

Register Name Size (bits) Address Offset R/W Description
CR 20 0x00 W Control Register
FFR 22 0x04 R/W First Failing Register
CMR0 32 0x08 W Comparison Mask Register 0
CMR1 32 0x0C W Comparison Mask Register 1
BDIR 1-32 0x10 W Break Delay Initialization Register
SEMSR 11 0x14 R SEM Status Register
SEMSSR 11 0x18 R/W SEM Sticky Status Register
SEMIMR 11 0x1C W SEM Interrupt Mask Register
WR 32 0x20 W Watchdog Register
RFSR 32 0x24 W Reset Failing State Register
CSCR 32 0x28 W Comparator Status Clear Register
CFIR 4 0x2C W Comparator Fault Inject Register

But however, I dont see a difference in FFRregsiter.

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