12-03-2014 04:54 AM
I have video processing application with interlaced video out (PAL or NTSC). According to product guides for IP cores: VID_IN_2_AXIS (pg043 v3.0), AXIS_VID_OUT (pg044 v3.0), VTC (pg016 v6.1) interlaced mode is supported and my question is how to use them in application with frame buffer (VDMA)?
Product guides pg043 and pg044 explain this situation on Figure 3-6. Sentence: “For systems with a frame buffer, the field ID input can come from any core containing a frame buffer”. How? I cannot find signal Field ID on VDMA (v6.2) IP core. Maybe Field ID is not mandatory in AXIS application… Please I need little clarification about this.
Picture below represent simplified diagram of my test video processing implementation on ZYNQ 7Z020.
TPG generate test pattern in resolution 576p50, VDMA receive 576p frame and I need to output video frame in 576i50 format. Please where I can find some examples or hints how to set IP cores to work in interlaced mode.
Thanks in advance,
12-03-2014 05:36 AM
The AXI VDMA is commonly used as a simple frame buffer in video systems. However, the core has a number of more advanced features enabling the designer to implement more interesting functionality with minimal (or zero) additional external logic. In this example, a simple video interlacer is built using only the AXI VDMA, requiring no additional hardware or software overhead beyond that which is required for a simple three frame buffer. Progressive-to-interlaced conversion is possible using the AXI VDMA because the core provides separate programming of hsize and stride registers. The best way to think about these two settings is that the HSIZE is the active horizontal size of the video frame that you wish to transfer and stride is the location in memory where each line starts with respect to the previous line. Commonly, stride is set equal to hsize (for simplicity and minimal memory footprint) or the next power of two greater than hsize (for performance) on both read and write sides of the AXI VDMA. In order to accomplish progressive- to-interlaced conversion, the write side stride is still set equal to hsize, but the read side stride is set to two times hsize. For example, to accomplish 1080p to 1080i conversion, s2mm_hsize = s2mm_stride = 1920 and mm2s_hsize = 1920 but mm2s_stride = 2*1920 = 3840. Note that you will also need to set mm2s_vsize = s2mm_vsize/2 or 540 for the 1080p to 1080i conversion example above. By setting up the VDMA this way, the read side of the core will automatically skip every other line and will only send out half the frame (i.e. one field) per write frame period, presenting a proper interlaced stream. In order to verify the behavior of our progressive -to-interlaced converter, the progressive input data is created using the Test Pattern Generator and the interlaced output data is sent from the VDMA, through AXI Stream to Video and Video TX to SDI Bridge cores, and finally to an SDI transmitter on the TB-FMCH-3GSDI2A FMC card attached to the KC705. An SDI sink can be used to view the output video. Configuration and control of the system is accomplished via software running on a microblaze soft processor. Specifically, it handles control of the AXI VDMA, Test Pattern Generator, GPIO for SDI mode selection, and the Video Timing Controller. The software also provides a user interface via UART which allows the user to select from various supported resolutions and test patterns on the fly.
12-03-2014 05:49 AM
Check below links where you can get various reference designs.
12-04-2014 03:04 PM
thanks for reply! I will try this as soon as possible! :)
10-05-2017 10:37 PM
I have a question
I agree Hsize and stride changes will make interlaced video from VDMA.
In my project, progressive video stream and through the vidtoaxi and vdma and then axitovid with vtc(not detection mode only generate mode)
I could get the good result but sometimes my interlaced output even/odd line shows wrong order so jigsaw image.
In SDK, read stride 2xhsize and each frame buffer(index) memory entry point is different because of interlaced set(once even once odd)
Do you have any ideas?