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grando
Observer
Observer
5,432 Views
Registered: ‎09-15-2009

How to hold the execution of Microblaze in a multicore system

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Hi folks,

 

I'm developing a multicore system where one processor works as a bootloader for other processors.

The idea is:

 

Processor 0 runs a program stored at BRAM. Other processors will run programs stored in SDRAM.

Processor 0 assign a program to another processor by loading the program to its respective SDRAM address space.

 

My question is: how to keep the other processor in a "hold" modus untill the Processor 0 has loaded the entire program to RAM?

 

I've been thinking about individual reset signals to each processor, controlled by Processor 0 (when the program is loaded, the reset is released) but I'm not sure if there is another better solution...

 

Does anyone has a suggestion about it?

 

Thanks in advance,

 

Carmela

 

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goran
Xilinx Employee
Xilinx Employee
6,689 Views
Registered: ‎08-06-2007

Hi,

 

Since you can't let any processor to start to execute before you downloaded the programs to SDRAM, you need to control each processors reset signal.

I would add a GPIO which drive a reset signal to each processor.

 

Göran

 

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goran
Xilinx Employee
Xilinx Employee
5,413 Views
Registered: ‎08-06-2007

Hi,

 

If you only do this once, you can have a shared memory which each of the processor reads until it gets a value which means "start to execute".

If you don't want to have shared memory, you can connect a FSL from processor 0 to each of the other processors.

If the other processor does a blocking get, they will be halted until processor 0 do a put for each processor.

 

If you need to repeat this many times with new programs for the other processors, you need to either interrupt each of them or add some polling mechanism in the programs that they run. 

 

Göran

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grando
Observer
Observer
5,407 Views
Registered: ‎09-15-2009

Hi,

 

thank you for your reply!

It should be possible to load any program more then once for the same processor.

However just this processor 0 is suposed to have any BRAM. The others should work exclusively with the SDRAM.

 

It seems to me that your solutions supose that the other processors run some kind of bootloop initialized in BRAM. Since this is not the case, when the system starts, SDRAM has not yet any program loaded and the other processors will execute any trash contained there, which is also not good....

Based on your suggestions, I could figure out some solutions considering that a program or bootloop is already running from SDRAM. But it is still not clear for me how a processor will jump to the start address of a program (and not run trash) when this is the first program loaded, unless I use such "reset" signals....

 

Carmela

 

 

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prateek_bhatt
Scholar
Scholar
5,402 Views
Registered: ‎08-21-2008

Hello.

There can be another option.

Processors can be made to interact with each other through mailbox IP.

If you want to hold processors other than procesor 0 then whatever you want to run through other processors in that you can create a loop in the beginning of every code.

Those loops can only be broken after you get an interrupt from processor 0.

You generate that interrupt in the beginning of your processor 0 code and you download this one after you have downloaded the remaining ones.


 

Message Edited by prateek_bhatt on 12-11-2009 04:24 AM
Best of luck.
--
Unlimited in my Limits.
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goran
Xilinx Employee
Xilinx Employee
6,690 Views
Registered: ‎08-06-2007

Hi,

 

Since you can't let any processor to start to execute before you downloaded the programs to SDRAM, you need to control each processors reset signal.

I would add a GPIO which drive a reset signal to each processor.

 

Göran

 

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grando
Observer
Observer
5,391 Views
Registered: ‎09-15-2009

Yes, that's what I thought...

 Nevertheless, your other sugestions will be helpfull in further developments!

 

Thank you all!

 

Carmela

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