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Registered: ‎09-19-2018

How to program ZYNQ UltraScale+ MPSoC PL efuse through Vivado Hardware Manager?

I have a XCZU4 device. I need to program the 32-bit-user-defined code (FUSE_USER) located in PL efuses.

According to UG908: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug908-vivado-programming-debugging.pdf, page 85, this can be done easily using "Program eFUSE Registers..." function from Vivado Hardware Manager, as shown below: 

Capture1.PNG

However, when I connect my hardware in Vivado Hardware Manager, I couldn't see this function at all as shown below. I am using Vivado 2018.3.

Capture2.PNG

I know there is a way to program PL efuse internally using MASTER-JTAG primitive according to XAPP1283: https://www.xilinx.com/support/documentation/application_notes/xapp1283-internalprogramming-bbram-efuses.pdf , but my harware is customized, not an evaluation board. Also this method seems much more complicated than the traditional way of using an external JTAG as mentioned in that document.

So can anyone tell me what is the correct way to program PL efuse for a UltraScale+ device? Thanks a lot!

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