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Observer
Observer
5,515 Views
Registered: ‎11-12-2013

How to route EMIO signals through PL logic

As in some examples of zc702, I could route EMIO to PL side package pins.

 

But, how can I route the EMIO signals through the PL logic. I couldn't find any examples about it.

 

It is said it can be routed through PL logic in the tutorials video on "MIO and EMIO configuration for Zynq7000", but HOW?

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Xilinx Employee
Xilinx Employee
5,511 Views
Registered: ‎07-01-2010

Hi ,

 

Can you please refer to the AR http://www.xilinx.com/support/answers/51786.htm

 

Let me know if this helps.

 

Regards,

Achutha

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Observer
Observer
5,495 Views
Registered: ‎11-12-2013

Hi achutha,

 

Thanks for your quick reply.

 

I had looked into the example "gio_mio_emio_axi". It just connects the EMIO signals to DS (LED).

 

Now , say I have made a combinational logic circuit in the PL. Then, can I use the EMIO signals as input to that logical circuit, without assigning the EMIO signals to any package pins?

 

Thanks,

Saurabh Nair

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Observer
Observer
5,468 Views
Registered: ‎11-12-2013

My mistake,

 

Only thing I had to do, was to map EMIO to a signal and use that signal in my VHD code.

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