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Observer
Observer
9,886 Views
Registered: ‎11-17-2013

How to set up the FIQ

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Hey,

 

I'm trying to figure out how to set up the FIQ on the zynq. I'm able to produce interrupts on the IRQ_F2P and the IRQ lines successfully, but the FIQ is not working.

 

I'm using the BSP generated drivers for the Interrupt controller to configure the FIQ. Am I on the wrong track? Basically I'm using the provided example code to set up the interrupts and I'm triggering the line from PL via an AXI GPIO block. I checked the PL side with an ILA and it's working. So it has to be something wrong in my software.

 

This is how the initialization looks like

 

int setupIRQ(u16 DeviceId)
{
	int Status;

	/*
	 * Initialize the interrupt controller driver so that it is ready to
	 * use.
	 */
	GicConfig = XScuGic_LookupConfig(DeviceId);
	if (NULL == GicConfig) {
		return XST_FAILURE;
	}

	Status = XScuGic_CfgInitialize(&InterruptController, GicConfig,
					GicConfig->CpuBaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	/*
	 * Perform a self-test to ensure that the hardware was built
	 * correctly
	 */
	Status = XScuGic_SelfTest(&InterruptController);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	/*
	 * Setup the Interrupt System
	 */
	Status = SetUpInterruptSystem(&InterruptController);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	Status = XScuGic_Connect(&InterruptController, XPS_FIQ_INT_ID,
            (Xil_ExceptionHandler)fiq_handler,
            (void *)&InterruptController);

    if (Status != XST_SUCCESS) {
        return XST_FAILURE;
    }

    XScuGic_Enable(&InterruptController, XPS_FIQ_INT_ID); return XST_SUCCESS; }

 

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Xilinx Employee
Xilinx Employee
13,458 Views
Registered: ‎08-01-2008

Re: How to set up the FIQ

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This example design tests for FIQ interrupt. This example is designed to work with axi_timer in PL to cause an FIQ interrupt. The interrupt from axi_timer is connected to IRQF2P[15]( IRQ ID91)
The processor only operates in secure state. The interrupt is set as group 0 interrupt as secure interrupts, signaled as FIQ to processor.
HW/SW was generated by Vivado 2013.4 and tested on ZC702 production board.
 
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It's up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs.
Limited support is provided by Xilinx on these Example Designs.
Implementation Details
Design Type
PS & PL
SW Type
Standalone
CPUs
Single CPU
PS Features
GIC
PL Cores
AXI Timer
Boards/Tools
ZC702
Xilinx Tools Version
Vivado 2013.4
Other details
The interrupt from axi_timer is connect to IRQ ID91
Address Map
 
Base Address
Size
Bus Interface
axi_timer
0x42800000
64K
S_AXI
Files Provided
sourceme.tcl
 Vivado project
gic_fiq_test.c
source code
                                                                         Block Diagram


 

 

Solution
 
Step by Step Instructions
1. Reproduce the design by source sourceme.tcl in vivado 2013.4
2. Create HDL wrapper/ Generate Bitstream
3. Export Hardware for SDK
4. In SDK, generate an empty application, import gic_fiq_example.c
5. Program PL using the Bitstream generated by vivado
6. Run the application
 
Expected Results
Interrupt information will be printed as below
 
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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9 Replies
Highlighted
Xilinx Employee
Xilinx Employee
13,459 Views
Registered: ‎08-01-2008

Re: How to set up the FIQ

Jump to solution
This example design tests for FIQ interrupt. This example is designed to work with axi_timer in PL to cause an FIQ interrupt. The interrupt from axi_timer is connected to IRQF2P[15]( IRQ ID91)
The processor only operates in secure state. The interrupt is set as group 0 interrupt as secure interrupts, signaled as FIQ to processor.
HW/SW was generated by Vivado 2013.4 and tested on ZC702 production board.
 
Note: An Example Design is an answer record that provides technical tips to test a specific functionality on Zynq-7000.
A tip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools.
It's up to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design to fulfill his needs.
Limited support is provided by Xilinx on these Example Designs.
Implementation Details
Design Type
PS & PL
SW Type
Standalone
CPUs
Single CPU
PS Features
GIC
PL Cores
AXI Timer
Boards/Tools
ZC702
Xilinx Tools Version
Vivado 2013.4
Other details
The interrupt from axi_timer is connect to IRQ ID91
Address Map
 
Base Address
Size
Bus Interface
axi_timer
0x42800000
64K
S_AXI
Files Provided
sourceme.tcl
 Vivado project
gic_fiq_test.c
source code
                                                                         Block Diagram


 

 

Solution
 
Step by Step Instructions
1. Reproduce the design by source sourceme.tcl in vivado 2013.4
2. Create HDL wrapper/ Generate Bitstream
3. Export Hardware for SDK
4. In SDK, generate an empty application, import gic_fiq_example.c
5. Program PL using the Bitstream generated by vivado
6. Run the application
 
Expected Results
Interrupt information will be printed as below
 
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

Highlighted
Observer
Observer
9,864 Views
Registered: ‎11-17-2013

Re: How to set up the FIQ

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Thanks, this solved my problem :)

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Highlighted
Observer
Observer
9,800 Views
Registered: ‎07-29-2014

Re: How to set up the FIQ

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hey,

 

i also try to connect an axi_timer interrupt to nFIQ. I'm also able to produce interrupts on the IRQ_F2P but with FIQ it doesn't work.

The example above is not clear for me because it uses IRQ_F2P again, but i want only connect the interrupt to Core0_nFIQ.  Maybe i have missed something. I  would  be grateful for any advice thx.

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Highlighted
Observer
Observer
9,786 Views
Registered: ‎11-17-2013

Re: How to set up the FIQ

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Heres are some parts of my files.

 

Setup the GIC:

int SetUpInterruptSystem(u16 DeviceId)
{
	int Status;

	/*
	 * Initialize the interrupt controller driver so that it is ready to
	 * use.
	 */
	GicConfig = XScuGic_LookupConfig(DeviceId);
	if (NULL == GicConfig) {
		return XST_FAILURE;
	}

	Status = XScuGic_CfgInitialize(&InterruptController, GicConfig,
					GicConfig->CpuBaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}


	/*
	 * Perform a self-test to ensure that the hardware was built
	 * correctly
	 */
	Status = XScuGic_SelfTest(&InterruptController);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	return XST_SUCCESS;
}

 

Here's how my simplified FIQ setup routine looks like:

void setupFIQ(void) {
	//struct pt_regs regs;

	/* initialize FIQ registers */
	/*regs.ARM_r8 = (long)XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR;
	regs.ARM_r9 = (long)XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR+0x04;
	regs.ARM_r10 = (long)&stop;
	set_fiq_regs(&regs);*/

	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT,
			(Xil_ExceptionHandler) fiq_handler,
			&InterruptController);

	Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ);
}

The methods to set the registers are taken from the linux kernel.

 

Your handler should look similar to this:

void fiq_handler(void *CallbackRef)
{
	// do useful stuff
}

 

Call setupInterruptSystem first, then setupFIQ.

 


I hope this helps, otherwise report back.

 

Regards, Marcel

Highlighted
Observer
Observer
9,707 Views
Registered: ‎07-29-2014

Re: How to set up the FIQ

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Hi Marcel,

 

thank you very much for your reply. Your hint helped me a lot and now it works fine.  Another question have you ever tried to catch such an interrupt via linux? 

 

Regards, Georg

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Highlighted
Observer
Observer
9,635 Views
Registered: ‎11-17-2013

Re: How to set up the FIQ

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Yes I did. Here's the thread about it:

http://forums.xilinx.com/t5/Embedded-Linux/Requesting-privat-interrupts-in-kernel-driver-fails/td-p/497358

Unfortunately I wasn't successful. It seems that the private interrupts aren't that easy to handle in linux as the "normal" ones.

 

If you are able to figure it out, I'd be glad if you'd let me know how you did it.

 

Regards, Marcel

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Participant
Participant
9,461 Views
Registered: ‎10-12-2009

Re: How to set up the FIQ

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Hi,

Did you try to run this example using XPAR_FABRIC_AXI_TIMER_0_INTERRUPT_INTR on cpu1? I am trying but without success. Any idea?

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Visitor
Visitor
2,061 Views
Registered: ‎12-05-2018

Re: How to set up the FIQ

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it work well in Single CPU.my board zc706 has 2 cpu.I nterrupt may ocurr on cpu1, how can i clear interrupt.      thanks.

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Highlighted
Moderator
Moderator
1,973 Views
Registered: ‎07-31-2012

Re: How to set up the FIQ

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Hi,

 

You need to set clear interrupt register. Please that particular register in user guide on interrupt controller.

 

Regards

Praveen


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