How to transform this design into KC705 using a Microblaze?

[daryon]

Hi,

FYI : I am using Vivado 2017.3 targeting a KC705 board including a Kintex-7 (xc7k325t) FPGA.

I am trying to read data from DDR3 and load it to a FIFO and then send the read data for JESD204 to be read out by DAC.

Within my search, I found that Xilinx has provide a design strategy here, that implements an AXI DMA and FIFO on a Zynq device which has a PS and PL part.

I am trying to transform this design to be compatible with KC705 board and replace the Zynq Processing System with Microblaze. I cannot get a functional design. Can anybody help me to solve this issue?

Here is the design schematic provided by Xilinx:

Thanks and Regards,

Daryon

[tedbooth]

UG913 has some info about using microblaze on the KC705 board.

https://www.xilinx.com/support/documentation/boards_and_kits/k7_emb/2013_2/ug913-kc705-getting-started.pdf

[pvenugo]

Hi @daryon,

You got to do following steps-

1) re-target the Vivado project to KC705 evaluation board at settings.

2) Remove Zynq PS, Processor System Reset IPs.

3) Update rest of IP to KC705 as it will be prompted.

3) Add Microblaze and do connection automation.

Refer to block diagram in http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html 

Regards

Praveen

[savula]

Hi @daryon,

This is not that straight forward, because you need the MIG IP in case of Micro blaze which is not needed in case of Zynq because the Zynq as it included the DDR controller in it. replace the Zynq with Micro blaze and add the MIG IP and then try.

Best Regards,
Srikanth
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[daryon]

Hi @savula, @pvenugo, and @tedbooth,

Thanks for your replies. Can you please have a look on my recent post regarding this issue which I could solve some part of the problem but stuck in the final result.

Thanks for your kind consideration and help.

Daryon