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qwerty-off
Visitor
Visitor
413 Views
Registered: ‎09-20-2019

How to use PL DDR as Normal (not Device) memory

Hi,

I connected PL DDR to Zynq through the AXI GP Master. When I write or read aligned data, for example uint32 at addresses 0x..00, 0x..03 ... everything works well. When I try to write uint32 at 0x..01, the system crashes. As I understand it, Zynq uses PL DDR as Device memory in which operations at unaligned addresses are impossible. Is there any way to solve this problem?

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3 Replies
393 Views
Registered: ‎07-23-2019

 

There might be an option somewhere either in the MIG IP or the software... but the first that comes to my mind is writing bytes instead. Is that something that would fit into your strange scheme of memory usage?

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qwerty-off
Visitor
Visitor
388 Views
Registered: ‎09-20-2019

I tried to describe the problem in more detail. The error occurs if I use the structure:

typedef struct {
uint8_t a;
uint32_t b;
} sctructtype;

This working good:

typedef struct {
uint32_t a;
uint32_t b;
} sctructtype;

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369 Views
Registered: ‎07-23-2019

What if you define an union like this?

typedef union {
    struct{
        uint16 a:
        uint32 b;
    };
    struct{
        uint8 byte[6];
    }
} union_t;
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