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jasmine
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Registered: ‎10-09-2020

How to use the ACP port to read from and write to L2 cache?

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Hi all,

I am using Ultra96 v2 board (Zynq UltraScale+ MPSoC) and I am new to this board. I am trying to create a simple design to test the data transfer between PL and L2 cache using the ACP port. My problems include the difference between the HP port and the ACP port regarding functionality and usage.

1. With regard to functionality, I know that the ACP port can access the L2 cache. From my understanding, I need to provide a DDR address, then the HP port will access DDR, while the ACP port will first access L2 cache and then DDR. Is that right?

2. My major problem is the usage of the ACP port. I created a simple IP using vivado HLS (vector addition), and created block design using vivado (I used "run block automation" and "run connection automation"), then I created my ipynb file to run on the FPGA. It did work for the HP port and I got the right results. According to my understanding on 1, I do not need to change the HLS code and the ipynb code if I want to use the ACP code. Is that right? Then I tried. I only chose different PS-PL interfaces (I chose S_AXI_ACP when re-customizing IP), and all the other operations maintained the same. Specifically, I also used "run block automation" and "run connection automation". It successfully generated bitstream, but when running the program, it did not do the vector addition. I do not know the reasons...

My HLS code, ipynb code and the block design are as follows:

HLS:

 

void vec_add(int *in1, int *in2, int *out) {

#pragma HLS INTERFACE m_axi depth=256 port=in1 offset=slave
#pragma HLS INTERFACE m_axi depth=256 port=in2 offset=slave
#pragma HLS INTERFACE m_axi depth=256 port=out offset=slave
#pragma HLS INTERFACE s_axilite port=return bundle=control

    int tmp_in1[10];
    int tmp_in2[10];
    int tmp_out[10];

    for(int i = 0; i < 10; i++) {
        tmp_in1[i] = in1[i];
        tmp_in2[i] = in2[i];
    }

    for(int i = 0; i < 10; i++) {
        tmp_out[i] = tmp_in1[i] + tmp_in2[i];
    }

    for(int i = 0; i < 10; i++) {
        out[i] = tmp_out[i];
    }
}

 

 

ipynb file:

 

import sys
import os
import math
import time
import numpy as np
import cv2
import pynq
import ctypes

overlay = pynq.Overlay('design_1.bit')
xlnk = pynq.Xlnk()
nn_ctrl = overlay.vec_add_0
print('got nn accelerator!')

overlay = pynq.Overlay('design_1.bit')
xlnk = pynq.Xlnk()
nn_ctrl = overlay.vec_add_0

interval_time = 0
total_time = 0
total_energy = 0

rails = pynq.get_rails()

start = time.time()    
recorder = pynq.DataRecorder(rails["5V"].power)

with recorder.record(0.05): 
    nn_ctrl.write(0x10, in_buffer0.physical_address)
    nn_ctrl.write(0x18, in_buffer1.physical_address)
    nn_ctrl.write(0x20, out_buffer.physical_address)   
    nn_ctrl.write(0x00, 0x01)
          
end = time.time()
t = end - start

print('in1: {}\nin2: {}\nout: {}'.format(in_buffer0, in_buffer1, out_buffer))

 

 

Design block:

jasmine_0-1609216304563.png

 

And also some options:

jasmine_0-1609216472469.png

 

 

Thanks in advance! 

1 Solution

Accepted Solutions
kawazome
Adventurer
Adventurer
1,541 Views
Registered: ‎04-02-2014

Using ACP is not that difficult. Please note the followng two points.

* AXI Signal (AxCACHE and AxPROT)
* cache-line friendly transactions

1. AXI Signal (AxCACHE and AxPROT)

See the Xilinx Wiki for more information.

* https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Coherency#ZynqUltraScaleMPSoCCacheCoherency-3.AXISignals

To change the values of these signals in a component made with Vivado-HLS, do it from the Vivado Project.
Open the Vivado Project and select Open Block Design.
Right-click on the component you created in Vivado-HLS, then click Custmize Block ... Set the PROT value and CACHE value as follows:

PROT value "010"
CACHE value "1111"


2. cache-line friendly transactions

Quoted from [AR#66643](https://www.xilinx.com/support/answers/66643.html)

> The ACP interface on Zynq UltraScale+ MPSoC accepts only the following (cache-line friendly)transactions.
> Masters targeting ACP should account for these limitations:
>
> * 64-byte aligned 64-byte read/write INCR transactions.
> All write-byte strobes must be the same (either enabled or disabled).
> * 16-byte aligned 16-byte read/write INCR transactions.
> Write-byte strobes can have any value.
>
> All other transactions return an SLVERR response.

It can be little to meet this constraint with Vivado-HLS. I don't know how to this.

Instead, I created the ZynqMP-ACP-Adapter.
ZynqMP-ACP-Adapter is an adapter to connect AXI Master to ZynqMP ACP.
The adapter then splits any burst-length transaction into several 64-byte or 16-byte transactions.
For details, please refer to the following URL:

https://github.com/ikwzm/ZynqMP-ACP-Adapter

 

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7 Replies
jasmine
Visitor
Visitor
1,592 Views
Registered: ‎10-09-2020

Can anyone give me any suggestions on my case or maybe some tutorials about ACP port? Thanks very much!!!!

0 Kudos
kawazome
Adventurer
Adventurer
1,542 Views
Registered: ‎04-02-2014

Using ACP is not that difficult. Please note the followng two points.

* AXI Signal (AxCACHE and AxPROT)
* cache-line friendly transactions

1. AXI Signal (AxCACHE and AxPROT)

See the Xilinx Wiki for more information.

* https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Coherency#ZynqUltraScaleMPSoCCacheCoherency-3.AXISignals

To change the values of these signals in a component made with Vivado-HLS, do it from the Vivado Project.
Open the Vivado Project and select Open Block Design.
Right-click on the component you created in Vivado-HLS, then click Custmize Block ... Set the PROT value and CACHE value as follows:

PROT value "010"
CACHE value "1111"


2. cache-line friendly transactions

Quoted from [AR#66643](https://www.xilinx.com/support/answers/66643.html)

> The ACP interface on Zynq UltraScale+ MPSoC accepts only the following (cache-line friendly)transactions.
> Masters targeting ACP should account for these limitations:
>
> * 64-byte aligned 64-byte read/write INCR transactions.
> All write-byte strobes must be the same (either enabled or disabled).
> * 16-byte aligned 16-byte read/write INCR transactions.
> Write-byte strobes can have any value.
>
> All other transactions return an SLVERR response.

It can be little to meet this constraint with Vivado-HLS. I don't know how to this.

Instead, I created the ZynqMP-ACP-Adapter.
ZynqMP-ACP-Adapter is an adapter to connect AXI Master to ZynqMP ACP.
The adapter then splits any burst-length transaction into several 64-byte or 16-byte transactions.
For details, please refer to the following URL:

https://github.com/ikwzm/ZynqMP-ACP-Adapter

 

View solution in original post

jasmine
Visitor
Visitor
1,429 Views
Registered: ‎10-09-2020

Thank you very much!

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jasmine
Visitor
Visitor
1,409 Views
Registered: ‎10-09-2020

But it seems that I cannot set the PROT value and CACHE value using Vivado (by clicking Customize Block...). What should I do?

jasmine_0-1609734270459.png

 

kawazome
Adventurer
Adventurer
1,402 Views
Registered: ‎04-02-2014

What is Ultra_net? Isn't the component you made vec_add_0?

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jasmine
Visitor
Visitor
1,368 Views
Registered: ‎10-09-2020

Oh sorry... I used another project ultra_net which uses AXI Stream interface... Sorry... I can now set the values for vec_add_0.

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joe306
Scholar
Scholar
761 Views
Registered: ‎12-07-2018

Hello, would you mind sharing your project? I'm very interested in the ACP port and am using the Zynq Ultrascale+ MPSOC. Is HLS required?

Thank you

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