cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant
Participant
352 Views
Registered: ‎10-24-2018

How to use the AXI Switch in "control register routing" mode?

I have the XDMA core instantiated with AXI lite Master enabled.  Using it with the Xilinx provided linux drivers.

I want to use the AXI Lite Master connection to an AXI stream Interface( 1 slave, 2 Master) to control the switching. 

In PG085 there is an example on page 28 but i'm not sure how to command the switch from the AXI Lite Master

 

From PG085:

To configure a 4x4 switch where MI0 is sourced from SI1, MI1 is unused, MI2 is sourced from
SI3 and MI3 is sourced from SI0, use the following code example:
# Setup registers
Write address offset 0x40, Data 0x1
Write address offset 0x44, Data 0x8000_0000
Write address offset 0x48, Data 0x3
Write address offset 0x4C, Data 0x0
# Commit registers
Write address offset 0x0, data 0x2

0 Kudos
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
254 Views
Registered: ‎10-04-2016

Re: How to use the AXI Switch in "control register routing" mode?

Hi @ndnsoulja ,

Could you clarify your question?

I'm not sure if you are asking:

1. How to send PCIe read/write instructions to target the AXI Switch control registers.

Or

2. How to set the registers in the AXI Switch with your desired configuration.

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Participant
Participant
232 Views
Registered: ‎10-24-2018

Re: How to use the AXI Switch in "control register routing" mode?

@demarco 

I'm curious about number 2

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
206 Views
Registered: ‎10-04-2016

Re: How to use the AXI Switch in "control register routing" mode?

Hi @ndnsoulja ,

Could you elaborate on what you find confusing? The usage example in PG085 is kind of like pseudo-code to explain the sequence of memory writes a processor would need to perform to the AXI4-Stream Switch registers for the configuration described.

Perhaps you can explain what you are trying to do and we can walk through how you would program the switch.

Regards,

Deanna

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos