cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
TTC163
Visitor
Visitor
229 Views
Registered: ‎10-28-2020

How to write and read data to flash without Linux

Hi,

The board I use is Zedboard ZYNQ-7000, and my Vivado version is 2016.4

I am wondering how to write and read data to flash on baremetal application and SDK but not with Linux kernal

I've found AXI Quad SPI this IP for flash read/write but not sure how to configure it and how to determine the constraint file

The document said that Standard, Dual, and Quad modes all support making memory device as a slave. However, when I pick the standard mode, there is no option for selecting slave device

 

For testing this IP, I choose Quad mode, and use the constraint file provided by the document

It turns out that the design fail while generating bitstream. The following is my block design, constraint file and the error message

flash_error.PNG

 

 

 

# You must provide all the delay numbers
# CCLK delay is 0.5, 6.7 ns min/max for K7-2; refer Data sheet
# Consider the max delay for worst case analysis
set cclk_delay 6.7
# Following are the SPI device parameters
# Max Tco
set tco_max 7
# Min Tco
set tco_min 1
# Setup time requirement
set tsu 2
# Hold time requirement
set th 3
# Following are the board/trace delay numbers
# Assumption is that all Data lines are matched
set tdata_trace_delay_max 0.25
set tdata_trace_delay_min 0.25
set tclk_trace_delay_max 0.2
set tclk_trace_delay_min 0.2
### End of user provided delay numbers
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay] [get_pins -hierarchical *startup*/*usrcclko]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
#create_generated_clock -name clk_sck -source [get_pins -hierarchical*axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
# Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCKfalling edge
# Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_1_IO] -clock_fall;
set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_1_IO] -clock_fall;
# Data is captured into SPI on the following rising edge of SCK
# Data is driven by the IP on alternate rising_edge of the ext_spi_clk
set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_1_IO];
set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_1_IO];

 

 

 

flash_error_msg.PNG

 

I'm not sure is the Quad mode suitable for memory read/write, and the main problem is that I also have no idea of using the IP to fulfill my request

Can anyone give me some example, tutorial or driver of this IP?

Or does anyone know how to configure it if I just want to read/write some data into flash?

Or is there any other solution for this problem?

 

Thanks!

Tags (2)
0 Kudos
2 Replies
ibaie
Xilinx Employee
Xilinx Employee
147 Views
Registered: ‎10-06-2016

Hi @TTC163 

For Zynq-7000 there is no need to use the AXI SPI IP as the processing subsystem already has the QSPI controller built in. I'm not used to Zedboard and it has been a while since I used 2016.4 release (any reason to use such an old release?), but I would bet that the board automation will configure the QSPI in the PS automatically.

Once the design is exported, in the SDK there are some examples for the QSPI driver where you can do read and write operations to the flash device in baremetal or standalone mode.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
0 Kudos
ibaie
Xilinx Employee
Xilinx Employee
144 Views
Registered: ‎10-06-2016

Hi @TTC163 ,

As expected a quick testing on 2016.4 release shows that QSPI is configured by default in Single mode:

image.png

This controller is connected to the flash device present in the Zedboard and as mentioned earlier the standalone examples should work straightaway.

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
0 Kudos