03-19-2021 12:17 AM - edited 03-19-2021 12:19 AM
I have a question, so I am posting.
The FPGA board I use is zc706. / Vivado 2017.4
I designed the logic in PL and sent the operation result to PS through interrupt_signal.
PS is designed to send signals to various processes and PLs.
After the bit-stream is completed, it has been confirmed that the desired result comes out when the operation is executed in the SDK.
At this time, the input frequency of the ZYNQ7 Processing System was set to 33.333333MHz and the PL Fabric Clocks were set to 100MHz.
However, in order to perform data processing more quickly, looking at the input frequency standard, it was confirmed that it is possible up to 60MHz.
Therefore, the Input Frequency was set to 60MHz and the PL Fabric Clocks were set to 90MHz.
However, in this case, even the bit-stream was performed without problems, but when the SDK is executed, the result of data processing through UART communication is not output to the terminal.
Does anyone know how to fix it?
04-14-2021 11:34 AM - edited 04-14-2021 01:23 PM
The way you describe things indicates that you are quite lost. Consequently:
>Does anyone know how to fix it?
Not yet. Could you attempt to describe your question and the situation using conventional terminology?
Some helpful hints:
PS: Processing System (as opposed to PL for programmable Logic)
Also, are you changing the frequency of the clock going into the PS from the PCB? As in manually changing the oscillator, or reprogramming it if it is programmable?
Because the input frequency in the Zynq PS wizard is how you tell the tools the frequency the oscillator. It needs to be accurate in order for the wizard to calculate correct multipliers and dividers for generating requested frequencies (e.g., to the PL). It is not the method for changing the frequency, it is a method for telling the tools the input frequency.
To actually change the frequency you need to modify the board, or if there is a programmable oscillator on the board, reprogram it. Then, after that, you can come back to the PS wizard and tell it the frequency as you have provisioned external to Vivado.
More to the point. You probably shouldn't attempt to do this.
You can get a wide variety of frequencies going to the PL on the PL_CLK<X> signals by changing the requested frequencies and/or the internal PLLs, as your screen shot indicates. But don't mess with the input frequency of 33.3333 MHz unless you are modifying your devCard (or reconfiguring a programmable oscillator) .