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heedaf
Explorer
Explorer
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Registered: ‎06-25-2008

I2C Clock Speed

The I2C SCL clock speed on a Spartan 3e and Spartan 6 LXT is only about 330 KHz instead of the specified 400 KHz.  Does anyone know why and how to fix this?

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johnmcd
Xilinx Employee
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Registered: ‎02-01-2008

I'm not sure how you are seeing this limitation. I do know that SCL is derived from the core's bus clock and there needs to be an even divisor between the bus clock and 400KHz. So you may need to change your bus frequency or if you are using axi, you can just change the frequency of the core's axi clk.

 

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evgenis1
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Registered: ‎12-03-2007

Hi,

 

400KHz is the upper limit bound in the fast mode defined by the i2c spec. The actual speed can be any value up to 400.

 

Thanks,

Evgeni

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heedaf
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Registered: ‎06-25-2008

I need to get the bus speed as fast as possible.  I am using AXI but when I try changing the AXI bus speed I get an error from EDK. Can you point me to some documentation on how to do this?

Thanks,

DeWayne

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johnmcd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

You can use the 'ports' tab to change the axi clock for your spi core. If you can't find the axi clk for the core, make sure all filters are enabled.

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heedaf
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Registered: ‎06-25-2008

Thanks!  I changed the I2C clock speed to 500 KHz and now I'm getting 398 KHz.  In PLB, anything over 400KHz didn't have any effect so something has changed with AXI.

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johnmcd
Xilinx Employee
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Registered: ‎02-01-2008

Since you are using more than 400KHz you are outside of the spec for the core so support is limited.

 

You could modify the core on your own but it will not be supported by Xilinx. Copy the axi_iic core from edkInstall/hw/XilinxProcessorIPLib/pcores into your project's local pcore directory. The iic core is not a paycore so the hdl is clear text. Then diff the iic_control.vhd file with the plb version to see the changes that have taken place with the functions used to calculate the dividers. Note that you may also end up adjusting the setup and hold values on the iic interface.

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heedaf
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Registered: ‎06-25-2008

I would normally agree with you but something funny is going on.  If I put in 400 KHz the SCL output is only clocking at 330 KHz but if I put in 500 KHz I get the required output of 400 KHz.  Has anyone investigated what the problem is with the core?  Seems like my Spartan 3e had the same issue.

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johnmcd
Xilinx Employee
Xilinx Employee
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Registered: ‎02-01-2008

This post makes things clearer.

 

Please create a webcase and include your design.

 

Can you post the generics in this thread as found in the hdl/iic_...._wrapper.vhd file?

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