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Visitor
Visitor
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Registered: ‎11-14-2019

ID Width in AXI Interconnect RTL v1.7 limited to 8 bits ( AXI Slave )

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Hi,

 

I am trying to integrate AXI Interconnect RTL v1.7 as a standalone IP with the rest of my project. I am seeing that Xilinx provides a maximum of 8 bits as ID width for slave side in interconnect, is there any provision or an alternative where we can increase those bit count? I have a requirement of ID width as 12 bits.

 

Thanks.

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Moderator
Moderator
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Registered: ‎03-25-2019

Hi @nlotankar,

We don't recommend to use the AXI Interconnect RTL V1.7 for new designs.

Please use AXI Interconnect V2.1 instead. Here it is the AR#60968 that explains how to use the V2.1 with your RTL project (non-block design).

Best regards,
Abdallah
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Scholar
Scholar
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Registered: ‎05-21-2015

@nlotankar,

You might be stuck here.

Many interconnect components require separate state machines (and possibly FIFOs) for each individual ID.  It makes sense therefore to limit the number of IDs that the interconnect has to deal with in order to keep resource usage reasonable.

The purpose of IDs is to allow out of order returns.  Is there a reason why you need more than 8-bits?

Dan

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Moderator
Moderator
141 Views
Registered: ‎03-25-2019

Hi @nlotankar,

We don't recommend to use the AXI Interconnect RTL V1.7 for new designs.

Please use AXI Interconnect V2.1 instead. Here it is the AR#60968 that explains how to use the V2.1 with your RTL project (non-block design).

Best regards,
Abdallah
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