cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
dje666
Voyager
Voyager
325 Views
Registered: ‎04-21-2017

IDT Clock-chip 8A34001 initial settings and post-boot setup

Dear Forum,

I have access to an ZCU208 RFSoC dev-kit. To use the zSFP interfaces I need to provide a ref-clk into the GTY quads that drive the zSFPs. The GTY-Quad ref-clocks are provided by an IDT chip 8A34001, but I can find no documentation that describes what clock frequencies (if any) the IDT 8A34001 chip is setup to generate from cold-boot, nor how to re-program this chip.

For the Q11_out and Q7_out clock sources that the 8A34001 chip generates....

1) What are the default output frequencies from a box-fresh cold-boot?

2) Does this chip rely on the MPSoC PS to configure it at every boot cycle, or are its settings retained between power cycles?

3) Is is possible to program the 8A34001 via an external programming unit and SW, or is the I2C interface from the MPSoC PS the only access point?

4) If the PS is the only programming access point, is there a bare metal application that I can run on the PS to program the 8A34001 device, prior to power cycling the dev-kit and then running my own project ?

Regards,

 

DJE666

Tags (4)
0 Kudos
1 Reply
idar
Visitor
Visitor
187 Views
Registered: ‎01-09-2020

Dear dje666 and all.

I am actually wondering about the same, and will therefore bump this question.
The quick reply to you dje666 is that the 8a34001 can indeed be programmed with the SCUI Windows-interface which you may find in the ZCU208 files on the Xilinx webpage. You may see below which file I have used to get 10G networking going on the SFP+ ports.

Could anyone, or perhaps a Xilinx employee, guide to some help on programming the 8a34001-clock on the ZCU208 and ZCU216 boards using petalinux and the BSP? Such a section is missing for the ZCU208 and 216 cards in the Confluence webpage...

For the ZCU216 I have found the file:
<petalinux-project>/components/plnx_workspace/device-tree/device-tree/zcu216-reva.dtsi
where on lines 394-398 there is a section that perhaps could be used to program the 8a34001 clock?
My wish would be to program it with the settings found in the "8A34001_20191007_100MHz_CLK0_156MHz.txt" file provided with the SCUI, as this configures the SFP+ connectors for 10G networking. However, there are no comments in the code as to what should be written there...


I would be very grateful for any guidance on this.

Best regards,
Idar

0 Kudos