IIC lockup on ArtyS7-50 Rev B with Pmod Hygro

[cvpeck]

Hi all,

I'm attempting to get a simple I2C demo running using an ArtyS7-50 and a Pmod Hygro.

Vitis / Vivado 2020.1.1

It seems the I2C bus is hanging on initialisation of the Hygro unit -

		/*
		 * Clear the latched interrupt
		 * status for the bus not busy bit which must be done while
		 * the bus is busy
		 */
		StatusReg = XIic_ReadReg(BaseAddress,  XIIC_SR_REG_OFFSET);
		while ((StatusReg & XIIC_SR_BUS_BUSY_MASK) == 0) {
			StatusReg = XIic_ReadReg(BaseAddress,
						  XIIC_SR_REG_OFFSET);
		}

 I've seen other people fix this by increasing the inertial_delay parameter for the I2C driver, but I am using the stock standard AXI_I2C_LITE as part of a Microblaze design.

Can anyone offer advice as to how to fix this as I am still learning!

Thanks,

Chris

[venui]

Hi,

can you please use dynamic flow and check it once.

Regards,

Venu

[cvpeck]

Hi, I'm not familiar with dynamic flow. Are you able to elaborate a little?

[venui]

Hi,

Please use the following example https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/iic/examples/xiic_dynamic_eeprom_example.c

Regards,

Venu