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Observer
Observer
438 Views
Registered: ‎07-02-2019

ILA(integrated logic analyzer) cannot able to tab signals , I created a design with our custom IP integrated in PL section of ZCU102

Hi, 

I have created a design which consists of our own custom ip interfaced to the AXI4 and connected to the PS section of ARM A53 core, I created a bitstream and down loaded on to the target  platform hardware ZCU102 MPSOC eval board.

I was unable to tab the signals using ILA , please help me in capturing the signals of my custom IP.

WARNING: [Labtools 27-3361] The debug hub core was not detected.

Resolution:

  1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
  2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.

For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).

WARNING: [Labtools 27-3413] Dropping logic core with cellname:'Base_Zynq_MPSoC_i/ila_0' at location 'uuid_137E009D375E505199F372FA0C35BA1F' from probes file, since it cannot be found on the programmed device.

WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.

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Scholar
Scholar
425 Views
Registered: ‎08-07-2014

Re: ILA(integrated logic analyzer) cannot able to tab signals , I created a design with our custom IP integrated in PL section of ZCU102

@kranthi018,

Is the ILA core clock connected to the axi_clk?

Is the axi_clk a free running clock?

Can you see the ILA core signals in simulation?

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Observer
Observer
395 Views
Registered: ‎07-02-2019

Re: ILA(integrated logic analyzer) cannot able to tab signals , I created a design with our custom IP integrated in PL section of ZCU102

Hi,

ILA clk is connected to PL_clk of the processor core(Zynq _ultrascale_MPSOC)

PS section PL_clk  is connected to AXI_clk,S_ACLK,M_ACLK of the AXI interconnect(PS8_axi_peripheral).

I was unable to get the probed signals of the ILA.

Here by Iam attaching the block diagram representation and error what it is throwing.

 

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Observer
Observer
349 Views
Registered: ‎07-02-2019

Re: ILA(integrated logic analyzer) cannot able to tab signals , I created a design with our custom IP integrated in PL section of ZCU102

Hi Dpaul,
In my project ,ILA clk is connected to PL_clk of the processor core(Zynq _ultrascale_MPSOC)
PS section PL_clk is connected to AXI_clk,S_ACLK,M_ACLK of the AXI interconnect(PS8_axi_peripheral).
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Voyager
Voyager
339 Views
Registered: ‎03-28-2016

Re: ILA(integrated logic analyzer) cannot able to tab signals , I created a design with our custom IP integrated in PL section of ZCU102

@kranthi018,

In my experience, the PL_clk does not start running until the PS is initialized and running.  If you haven't done so already, try loading the bitstream and then launching a simple program on the PS.  A simple "Hello World" application would be sufficient to set up the PS and get it running.  From there the PS_clk should be active.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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