07-19-2019 03:25 AM
I have created a design which consists of our own custom ip interfaced to the AXI4 and connected to the PS section of ARM A53 core, I created a bitstream and down loaded on to the target platform hardware ZCU102 MPSOC eval board.
I was unable to tab the signals using ILA , please help me in capturing the signals of my custom IP.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'Base_Zynq_MPSoC_i/ila_0' at location 'uuid_137E009D375E505199F372FA0C35BA1F' from probes file, since it cannot be found on the programmed device.
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
07-19-2019 04:41 AM
Is the ILA core clock connected to the axi_clk?
Is the axi_clk a free running clock?
Can you see the ILA core signals in simulation?
07-19-2019 05:48 PM
ILA clk is connected to PL_clk of the processor core(Zynq _ultrascale_MPSOC)
PS section PL_clk is connected to AXI_clk,S_ACLK,M_ACLK of the AXI interconnect(PS8_axi_peripheral).
I was unable to get the probed signals of the ILA.
Here by Iam attaching the block diagram representation and error what it is throwing.
07-22-2019 05:04 AM
07-22-2019 06:41 AM
In my experience, the PL_clk does not start running until the PS is initialized and running. If you haven't done so already, try loading the bitstream and then launching a simple program on the PS. A simple "Hello World" application would be sufficient to set up the PS and get it running. From there the PS_clk should be active.