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Visitor
Visitor
6,415 Views
Registered: ‎02-24-2015

Implementation of a second Lmb Bram controller

In our design, using XPS, we have implemented a second Lmb Bram controller connected to a Microblaze.

Expectation is that the connections between the Microblaze and the controller will be the same as the first Lmb Ram controller.

But it differs!

 

Using PlanAhead after implementation (ISE) the primitive Pselect_mask_lmb is missing for the d_Bram_ctrl_2 and the net Lmb_select too (see attachement).

Are these signal and net needed for a correct Bram Controller implementation?

How to get two identical implementations of a Bram controller (the first one was automated with the Microblaze selection)?

 

The second implementation of the Bram Controller is not working on the target board but no error is generated by the tools.

Net_LMB_data.jpg
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Xilinx Employee
Xilinx Employee
6,294 Views
Registered: ‎08-02-2007

hi,

 

is there any specific reason to have a second lmb controller? how about increasing the size of the existing lmb?

 

--hs

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Visitor
Visitor
6,270 Views
Registered: ‎02-24-2015

Hi,

We want to allow up to 128kB of code for the Microblaze.

But for now it is not working on the target using ISE 13.3

 

Two points are strange:

1)as said before the first implementation has  one more control signal than the second one.

2)when looking at the .bmm file the first Bram is implemented one bit after on bit when the second one is 8 bits after 8 bits.

It is then impossible to manually unit them for data2mem.

 

Is there a way to manually choose the connected signals and the bit with size of the physical implementation of the memory?

The idea is to create a second Bram memory block exactly identical to the first one, but with a different size (8kB in the attached example).

 

Jacques

 

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