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Explorer
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Registered: ‎05-31-2015

Improper Flushing of microblaze cache

Hello,

   

    I have a DDR connected to one of ports of MPMC controller. The MPMC is made cache addressible region.The bss segment of my SDK application is stored in MPMC. When I update my variables it has to reflect in MPMC as well as DDR. So I use microblaze_flush_dcache.The values are correcltly updated when cache is disabled , but not updated when cache is enabled. But I want cache for improved performance.Below given is my program. Attached is .xmp project.

 

#include "xparameters.h"
#include "platform.h"
#include "mb_interface.h"
#define MINE_ADDRESS (XPAR_MPMC_0_MPMC_BASEADDR + 0x00000000)

int shalini;

unsigned int * MinePtr;
int main()
{

#if MICROBLAZE_EXCEPTIONS_ENABLED == 1
microblaze_enable_exceptions();
#endif

 

#if XPAR_MICROBLAZE_USE_ICACHE == 1
microblaze_invalidate_icache();
microblaze_enable_icache();
#endif

#if XPAR_MICROBLAZE_USE_DCACHE == 1
microblaze_invalidate_dcache();
microblaze_enable_dcache();
#endif

shalini=0x234;
MinePtr = (unsigned int *)MINE_ADDRESS;

*MinePtr = 0x347;
microblaze_flush_dcache();
shalini=0x454;
int i;
for (i=1;i<50;i++);
while(1){}
}

 

 

I find out the address of variable shalini from map file and read DDR memory. When cache is ON , I get value 0 ,when OFF I get value 0x454.I tried both write through and writeback cache , no effect. I dont know where am I going wrong. Please make suggestions in my hardware and software configurations.

 

Thanks in advance

 

With Regards

Shalini

 

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