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diverger
Adventurer
Adventurer
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Registered: ‎06-22-2018

Interface to a 3-wire SPI using Zynq-7's SPI at PS side

I need to interface to a PGA with 3-wire SPI, SCK, SDIO, and CS. I know Zynq-7 has two full-duplex SPI at PS side, that is, 4-wire SPI. I wonder if the hardware and SDK support the 3-wire SPI?  I'm now considering connect both MISO and MOSI to the SDIO pin, when read data, temply disable the MISO, does the SDK support this?

 

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hayk.petr
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Registered: ‎10-04-2018

How about putting buffer, something like:

 

  IOBUF #(
    .DRIVE(12), // Specify the output drive strength
    .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for the buffer
    .IFD_DELAY_VALUE("AUTO"), // Specify the amount of added delay for input register

    .IOSTANDARD("DEFAULT"), // Specify the I/O standard

    .SLEW("SLOW") // Specify the output slew rate
  )

  IOBUF_inst (
    .O(MOSI), // Buffer output
    .IO(SDIO), // Buffer inout port (connect directly to top-level port)
    .I(MISO), // Buffer input
    .T(CTRL) // 3-state enable input, high=input, low=output
  );
// End of IOBUF_inst instantiation

 

 

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