06-03-2016 05:04 AM
I'm trying to get an TI ADC08D1520 running at 3GSPS (8 bits per sample) connected to a ZYNQ7020 devices. The idea is to log the data to external DDR memory. But the more I work on this the more difficulties I see.
1) The ADC output gives 32-bits at 750MHz, are the LVDSs capable of this speed?
2) Is it possible to push this much data over the Zynq's High performance AXI slave port towards the DDR?
3) The internal PL also needs also to run at 750MHz, this seams like a lot, is this possible?
The idea is to make a very high speed oscilloscope with long sample logging time (hence the external DDR memory). A basic ADC data path is described in the attached PNG file.
Any thoughts on the above?
06-03-2016 07:13 AM
06-03-2016 01:01 PM
agree with muzaffer,
also have you looked at how much data you want to save,
zynq is limited in its amount of DDR on the zynq port,
putting a second ddr port on the PL , just for the adc samples bulk store gives you more at higher difficulty
06-06-2016 07:29 AM
Thanks for your replys.
We use the 32-bit DDR interface from the zynq to interface to 1GB of DDR memory (2x 512 chip)
Is it possible to combine 2 HPx slave ports into a 128 bits wide port? This way I could reduce the PL clock speed by 4 and allow for sub 250MHz operation. Basic idea is again added in the attached file.
Idea is to buffer 4 x 32 bits at 750Mhz and pass this to a sub 250MHz 128 bits AXI bus. Somehow combining 2 AXI HP slave interfaces into 1 virtual 128 bits wide axi HP bus. This data is then passed to the DDR memory via the Zynq DDR controller.
One goal of the project is to save as much data as possible so using data compression is not the first though. Also adding a second DDR controller is not possible as we do not have enough pins available. We we need a much bigger package. The adc interface is already using 34 LVDS pairs (=68 IOs)
Please feel free to comment on the above proposed solution. And if you have any other thoughts they are all welkom.
06-06-2016 09:00 AM
06-06-2016 10:23 AM - edited 06-06-2016 10:27 AM
rather than use 128 bit data ,
use mutliple streams / fifos between the PL and PS, and ping pong,
the AXI has a terrible single word access time, not bad bursts.
1 G of memory is not a lot to store data,
and the zynq can't support more natively,
and with the zynq using some of the bandwidth of the ddr, your on a hiding to nothing
You ask for thoughts
Your using a USD 800 plus ADC,
"its the wrong FPGA "...
04-18-2018 08:04 AM
I saw this message looking for other info. I realize the original is 2 years old, but perhaps others may benefit from this post.
I am working on a project using three ADCADC08D1520 ADCs operating at 8b 1.5GSPS with 2-channels (I&Q) interfacing to an XC7VX485T. Each of the 2-ADC channel inputs is 4-sample lanes, 8b each, for 32b of data every 375MHz clock period (1.5GHz/4). 2-ADC 8b sample lanes of channel-1 are valid on the rising edge of the clock, the other 2 on the falling, I.E. DDR rate of 750MHz. The 2nd ADC channel, Q, is captured identically to the 1st, I.
A Xilinx DDR receiver IP in the IO section of the FPGA is used for the data capture of the ADC's clocking at 375MHz. The 375MHz clock is from one of the ADCs and is used to create the FPGA fabric system clock at 375MHz. The clock domain crossing is accomplished via a FIFO with input at the ADC's clock and output at the fabric system clock.
So the fabric sees 4-lanes of data from each ADC channel every 2.7ns. I wonder if your application could use this front end sampler to store your samples in parallel at a reasonable clock rate.