Is it possible to introduce the delay between SPI clock and SPI Chip select in Zynq

[srinivasan]

Dear Xilinx Community,

I am making use of the existing SPI module which is available in Zynq via EMIO, I need to introduce the delay of 50 microseconds between the SPI clock and SPI chipselect, please let me know if there is any provision for doing this in Zynq platform in linux

Kindly do the needful as early as possible, as am wondering whether it can really be done using SPI module which is available in Zynq

Many Thanks in advance

[ericv]

The SPI controller support a delay between the CS going low and the 1st data bit transfer

That's in the Delay_reg0 register.

Refer to Appendix B (Registers Details) in the TRM

You could also use the SPI with manual chip select mode,

Both mode and CS values are in the SPI control register.

Gooing that way you validate the CS and can initiate the transfer as late as desired and end the transfer and then invalidate the CS as late as you need.

It shouldn't be that complex even with Linux.

1 - validate the CS

2 - call the Linux driver to perform the transfer.

3 - once done, invalidate the chip select.

Regards