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Registered: ‎11-01-2018

Issue with SPI MISO line

I am having an issue with the throughput of the SPI when I set up the FPGA as a slave.


If I use the SPI IP with no FIFO buffers then the communication will work fine for all clock frequencies provided that I add a 50us delay between byte transmissions.


Without this delay the MISO then many duplicate and erroneous bytes appear in between expected bytes that were loaded into the transmit buffer of the XSPI driver using XSpi_Transfer() in Microblaze.


If I add 256 bytes deep Tx and Rx FIFOs then:

    1. There is no longer a need for the 50us delay

    2. The SPI master will always receive the first byte sent from the FPGA twice. All other bytes are received as expected

    3. An SPI transmission cannot exceed the size of the FIFO or the last byte will just be constantly sent once max size is reached


To me, all of this points to a problem in the timing of the loading of data on the MISO line and the reading of data from the MOSI line. Can you help me find out how I could get rid of the 50us delay?



Here is my current setup:


The SPI setup:

    SPI CLK set to 5 MHz

    CLK polarity set to 1, phase set to 0.


I have set up the Quad SPI IP as a slave with:

    ext_spi_clk set at 80 MHz

    the SPI is set as standard mode, without the use of Performance nor XIP modes

    the frequency ratio set as 8


I have also set the timing constraints on the SPI ports:


    create_clock -period 200.000 -name spi_clk [get_ports SPI_CLK]

    set_output_delay -clock [get_clocks spi_clk] -clock_fall 3.000 [get_ports SPI_MISO]
    set_output_delay -clock [get_clocks spi_clk] -clock_fall -min -1.000 [get_ports SPI_MISO]
    set_input_delay -clock [get_clocks spi_clk] -min -0.500 [get_ports SPI_MOSI]


    200ns was chosen as I set the SPI master's clk as 5MHz at most.

    3 ns ( Tsu(MI) ) setup and 1 ns hold ( Th(MI) ) times for the MISO line were set based on the master's SPI timing diagram

    (please refer to images below)

    0.5 ns used as Vivado would fail to meet timing constraint for any larger value.






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2 Replies
Registered: ‎10-03-2018

Re: Issue with SPI MISO line

I identified the same problem with AXI Quad SPI 3.2 IP core in slave mode only when FIFO buffer option is enabled. There is a hardware or driver issue with AXI Quad SPI 3.2 IP core that needs to be solved. Same problem appears in new revision of this IP core. 

SPI Slave (AXI Quad SPI) always sends first byte twice from tx buffer.

This IP core is useless for most of applications without FIFO buffer. Xilinx need to solve this bug!

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Registered: ‎10-03-2018

Re: Issue with SPI MISO line

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