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Registered: ‎05-05-2015

Issue with SPI interface on Zynq Ultrascale+


I am working on a project where we are using a ZU11EG device on a Sundance PCIe platform and an FMC RF carrier from Panateq with ADRV9009 front end. I use Analog Devices example code and drivers to program the ADRV9009 chip through the ARM’s SPI interface, but I’m facing and inexplicable issue. Some Sundance platforms are able to program the RF front end with no problem, but others don’t. I have narrowed down the problem to ARM itself. On the failing Zynq devices, the SPI chip-select is not asserted when expected.

The SPI is used in Master mode and chip select is in forced mode and set by "XSpiPs_SetSlaveSelect" function. Data is transferred using "XSpiPs_PolledTransfer". "emio_spi0_ss_i_n" is tied to logic 1 via a constant block.

Below are two screenshots of an ILA capture with a good and bad device. I am running the exact same code on both platforms, and they use the exact same Zynq device, so I’m quite puzzled! The ARDV9009 chip select is connected to bit0 among the three chip selects coming out of the SPI. I have also included a screenshot of my block design. Any help is greatly appreciated!







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