JESD fix when TX and RX are far apart

[u6113500@anu.edu.au]

Hi all,

I have established the JESD link (8 lanes, 12.5gbps / lane). DAC and fpga are quite far apart ~15cm. This makes my link noisy and i get a lot of errors in the received data & ofter resync of the link.

To inprove BER I have turned on scrambler and I am using equalisation tools that come with the DAC

What could be done on the FPGA side to improve BER?

1) PG066 mentions that JESD ip core has two single bit signals for "Transmitter pre-cursor pre-emphasis control" & "Transmitter post-cursor pre-emphasis control" but does        not provide any discription.
    What exactly do they do?

2) JESD ip core has inbuilt JESD PHY ip core and it can set different channel attenuation for different losses. However, this block is read only. 
    How can I change channel attenuation to "High Loss" (30dB). 

3) Is there anything else that I can do to make my JESD link better?

Cheers,
Anton

[chibane-mit]

Hello,

Are you using an FPGA eval board? And if yes, which one is it?

Cherif

[u6113500@anu.edu.au]

Hi,

I am using a cusom build board with DAC39j84 and TE0808 "UltraSOM+" mounted on TEBF0808-04. DAC board  is connected to the FPGA board via FMC connector.

[orondard]

Hi Anton,

There are a lot of parameters which can have an impact on BER (crosstalk, impedance matching, parasitic capacitance…).
Improving BER means to mitigate these unwanted effects. The idea is to ease the work of DAC equalizers.

If you have access to good lab equipments. I suggest you to probe JESD signal as close as possible of DAC, while tuning transceiver parameters.
Note that, a dedicated IBERT core would certainly help to do so.
Then you will be able to get optimized MGT settings, that could be reinjected in transceiver configuration.

JESD IP does not give that much control. You may want to separate JESD IP from PHY and even use transceiver wizard to design your PHY (it is actually more straightforward as it seems to be).

Olivier

[u6113500@anu.edu.au · Accepted solution]

THis is what solved my problem and improved the eye diagram:
1) Separate JESD ip core and JESD PHY 
2) Enable "High Loss" in the advanced settings of the JESD PHY ip block

NOTE: you cannot connect txoutclk & rxoutclk from the JESD PHY to the tx_core_clk and rx_core_clkin the JESD PHY and JESD block directly as it will not be routable. 
Use BUFG_GT for both clocks.