JTAG for a custom processor

[leonardooalves]

Hi, I hope you are well.

I am trying to implement the Cheri Processor on Arty7-100 FPGA and operate it with the on-board DDR memory. I am new to Vivado, so I am to do it in a block design (check attached image).

However, the processor has an internal JTAG/Debug system, and I could not find any IP core that I can use for that purpose. I have been searching for it, but the JTAG to AXI Master and BSCAN to JTAG IPs does not seem to fit my case. Is there any JTAG IP core that I can use for the core shown in the image, or I need to build my own?

I would appreciate documentation about it as well.

Thank you for your help.

[stephenm · Accepted solution]

You need a bscan, and a bscan2jtag IP.

The BSCAN can be added in the debug bridge IP:

Then just add the bscan2jtag, and connect this as shown below:

[leonardooalves]

That is exactly what I am looking for. I also noticed it refers to the documentation, thank you very much for your help.