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noami9226@
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Registered: ‎10-31-2019

JTAG-to-AXI IP Core

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Is it possible to write a testbech code to simulate my design shown in the pictureee.jpg?

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markgraf
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Registered: ‎04-04-2018
You should be able to. Refer to chapter 5 in the PG for commands. If possible, generate example design and see what is done there.

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com

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markgraf
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Registered: ‎04-04-2018
You should be able to. Refer to chapter 5 in the PG for commands. If possible, generate example design and see what is done there.

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com

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markgraf
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Registered: ‎04-04-2018
It appears that the JTAG to AXI Master does not support simulation.
This is from the example design test bench:
$display("-------------------------------------------------------");
$display("JTAG_AXI do not support simulation");
$display("Test completed successfully");
$display("-------------------------------------------------------");
$finish;

The commands listed in chapter 5 must be for running on hardware.
I think you could simulate design, but you would need to use an AXI Traffic Generator in AXI4-Lite mode and add another MAster and SLave port to your interconnect.

Sorry for the misinformation.

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
noami9226@
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Registered: ‎10-31-2019
Many thanks to you.
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