12-27-2019 06:04 AM
I am using zybo z720 eval. board which is having zynq fpga, I have created block design with xilinx's "JTAG to AXI Master v1.2" ip core and "AXI IIC Bus Interface v2.0" in Zynq PL to access iic device using vivado 2017.4,So after opening hardware manager and programming of FPGA, I am using this command to read "create_hw_axi_txn -quiet -force rd_tx [get_hw_axis hw_axi_1] -address $addr -len 1 -size 32 -type read
run_hw_axi -quiet rd_tx", But i am not able to read-write through Jtag axi master because i am not getting "hw_axi_1" under FPGA in hardware manager, So please help me how to read and write using JTAG to axi master in Zynq PL.
Please find Fig 1: given below snapshot of my block design.
Please find Fig 2 given below snapshot of my hardware manager
Please find Fig 3 given below as reference how it should come in hardware manager
01-06-2020 08:31 AM
So in this case you are saying that you make a design with the AXI IIC IP. then you add the JTAG to AXI master debug core to take control of the IIC interface from your PL.
Then it seems the JTAG to AXI master is not present when you look in HW manager?
So what you don't say is what you end up with in the design after implementation, have you looked and seen that the Core is in the netlist?
If so are you pointing at the correct ltx file in hardware manager?
Have you tried checking the JTAG cable speed and slowing it down?