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lsisaxon
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Registered: ‎03-06-2018

LPDDR4 with Zu3EG

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Hi,

 

I have a question regarding the use of LPDDR4 memory on the ZU3EG. Since only 32-bit LPDDR4 is supported, does the operating system need to operate in 32-bit mode or does the DDR controller make it transparent to a 64-bit OS?

 

At the moment we are using the ZCU102 Evaluation board for early software implementation pending our hardware design. Since the eval board is running 64-bit DDR4 on ZU9EG, what are the potential obstacles that could arise when porting to ZU3EG + 32-bit LPDDR4 from the memory point of view?

 

Thank you.

 

Best regards,

Saxon

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allanherriman
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Registered: ‎01-08-2012

@lsisaxon wrote:

I have a question regarding the use of LPDDR4 memory on the ZU3EG. Since only 32-bit LPDDR4 is supported, does the operating system need to operate in 32-bit mode or does the DDR controller make it transparent to a 64-bit OS?


The DDR controller makes it transparent.  I understand that 64 bit accesses coming out of the AXI bus masters (e.g. CPUs, DMA) will be turned into pairs of 32 bit accesses by the ram controller.

Any assumptions made in software about 64 bit accesses being atomic will still be valid because the pair of 32 bit accesses can't be split by anything happening on the AXI side of the ram controller.

 


@lsisaxon wrote:

At the moment we are using the ZCU102 Evaluation board for early software implementation pending our hardware design. Since the eval board is running 64-bit DDR4 on ZU9EG, what are the potential obstacles that could arise when porting to ZU3EG + 32-bit LPDDR4 from the memory point of view?


The ram controller might need to be configured differently (which is typically done by the FSBL).

 

It's slower because twice as many beats on the ram interface will be needed to fill or flush a cache line.  The speed might also differ because you will be using a different clock frequency, but you didn't specify that.

 

I'm also guessing that it's smaller (since you have half the number of same-sized chips?) so that might affect the size of the applications you can run.

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allanherriman
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Registered: ‎01-08-2012

@lsisaxon wrote:

I have a question regarding the use of LPDDR4 memory on the ZU3EG. Since only 32-bit LPDDR4 is supported, does the operating system need to operate in 32-bit mode or does the DDR controller make it transparent to a 64-bit OS?


The DDR controller makes it transparent.  I understand that 64 bit accesses coming out of the AXI bus masters (e.g. CPUs, DMA) will be turned into pairs of 32 bit accesses by the ram controller.

Any assumptions made in software about 64 bit accesses being atomic will still be valid because the pair of 32 bit accesses can't be split by anything happening on the AXI side of the ram controller.

 


@lsisaxon wrote:

At the moment we are using the ZCU102 Evaluation board for early software implementation pending our hardware design. Since the eval board is running 64-bit DDR4 on ZU9EG, what are the potential obstacles that could arise when porting to ZU3EG + 32-bit LPDDR4 from the memory point of view?


The ram controller might need to be configured differently (which is typically done by the FSBL).

 

It's slower because twice as many beats on the ram interface will be needed to fill or flush a cache line.  The speed might also differ because you will be using a different clock frequency, but you didn't specify that.

 

I'm also guessing that it's smaller (since you have half the number of same-sized chips?) so that might affect the size of the applications you can run.

View solution in original post

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