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Participant
Participant
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Registered: ‎07-24-2017

LWIP connects with linkspeed 1000 with autonegotiate, but does not when forced to 1000

Hi everyone.

 

Here are the components I have in the system:

FPGA: xc7a100

Ethernet IP: Axi Ethernet Subsystem v6.2

PHY: Marvell 88E1512

FPGA to PHY interface : RGMII

PHY to PC interface : Copper

 

Here are the tools I use:

Vivado 2014.4, SDK 2014.4

Lwip stack : lwip140 v2.3

 

My problem: The system is working perfectly when I set the link speed option to autonegotiate or 100Mb or 10Mb. When it autonegotiates it gets a link speed of 1000. But when I set link speed to 1000 (CONFIG_LINKSPEED1000) from bsp settings, it stops receiving my messages. It does not stop working though, when I enabled UDP debug, I can see the broadcast messages that are sent by my pc just as it does in autonegotiate case. As far as I observed in CONFIG_LINKSPEED1000 case, it drops my messages, which are sent with a specific destination IP. Have you ever experienced such an issue? I can not blame any hardware component since it catches every broadcasted message, and it works fine with autonegotiation(autonegotiation results with 1000 also!). What might be the problem?

 

PS1: I am aware that xaxiemacif_physpeed.c is problematic for my PHY, but as far as I know it has issues with autonegotiation, and I have found a patch to overcome that autonegotiation problem. I did not touch any other utilities of that file.

 

PS2: I have full control over the PHY registers, both dynamically and at boot stage, if you have any ideas that requires direct access to PHY registers, do not hesitate to share.

 

Thank you for your attention.

Mustafa

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Highlighted
Participant
Participant
526 Views
Registered: ‎07-24-2017

Re: LWIP connects with linkspeed 1000 with autonegotiate, but does not when forced to 1000

Well, I have solved it. It is a timing issue, probably because of the lack of length matching on the lines between FPGA and PHY.

The patch I found for autonegotiation writes  0 to RGMII Transmit Timing Control bit of MAC Specific Control Register 2 on PHY configuration registers.(Alaska ® 88E1510/88E1518/88E1512/88E1514 Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver Datasheet - Public, Page 106, Table 109) Which disables internal delay of the transmit clock. In this case I can communicate.

 

When I set to force linkspeed to 1000, Xaxiemacif_physpeed.c writes 1 to that bit(RGMII Transmit Timing Control bit of MAC Specific Control Register 2) under  configure_IEEE_phy_speed(XAxiEthernet *xaxiemacp, unsigned speed) function: 

 

phy_val |= IEEE_RGMII_TXRX_CLOCK_DELAYED_MASK; // The mask is 0x0030
XAxiEthernet_PhyWrite(xaxiemacp, phy_addr, IEEE_CONTROL_REG_MAC, phy_val);

 

As long as I understand, UDP does some sort of handshaking before sending packets to a certain ID, and if that fails it does not send, the handshaking does not apply to broadcast packages(obviously). This is why I was able to catch broadcast packages, but lose direct packages when I have failure at transmit timings.

 

I rarely write under this forum, and I may not be aware of the rules, I don't know if I should leave these two messages here or if I should delete them. I would be glad if you inform me about this.

 

Thanks a lot for your attention.

Mustafa

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