I faced a problem while designing a system with large bram size (32 x 256K - WIDTH x DEPTH) on Zynq 7000 series (ZC706 board).
I tried to generate a single bram instance of simple dual port bram using block memory generator with width of 32 bits and depth around 256K which utilizes 232 block ram slices (total available 545). I uploaded data from DRAM to BRAM using bursts of 256 length (write operation working fine). While reading back the data from bram I got the data in anonymous order and also data bus flipped when address bus is carrying the same address.
So, I thought of having some sort of timing issue with the memory design. I tried to lower the operating frequency and tried upto 500 kHz but still the results are same i.e. data is anomalous and and bits getting flipped in non-uniform fashion.
Experiments performed to debug :
1. Lower frequency - 500KHz - 32 x 256K - Result - Failing to read
2. Nominal Frequency - 500KHz - 32 x 256K - Result - Failing to read
Banking Structure implementation:
I also tried to lower the bram size and analyze the behaviour and I found that we can have reliable read operations with bram size (32 x 64K) and data is in orderand works well even at 50MHz .
So I tried to bank the overall required memory i.e. (32 x 256K) into four banks of (32 x 64K) as I was getting correct data for lower bram size. But still after instantiating four small bram modules, It followed similar anomalous operation and unable to provide the correct data.
I think the problem is because of overall bram utilization by the system and it corrupts the data once a limit is reached but system uses less than 50% of total bram available and I couldn't figure out the root cause of the problem.
If anyone has encountered similar problem or can help me with this problem. Any help would be appreciated.