12-16-2013 01:43 PM
Simulating the CDCE949 TI Clock Device to Zynq SoC. I am seeing non-monotonic edges and I can't seem to smooth those out with different series resistance or impedance or distance. Any suggestions?
Using the LVCMOS_33_F_8_PSMIO model for the Zynq receive end.
I used some other devices as receivers in the model and they don't seem to have this problem.
12-17-2013 05:31 AM
I've tried 0 ohms and 50 ohms and 75 ohms and 100 ohms with combinations of transmission line impedances as well....the only thing that smooths it out is about 500 ohms :-P -- that was just a silly attempt to see what happens with a completely stupid series resistance...
I attached the 0 ohm version jpg here
12-17-2013 05:49 AM
I'm trying to understand why the signal at the Zynq end looks like it's in the middle of a transmission line rather than the end. With series termination at the source, I would assume you have no termination inside the Zynq? What is the IO standard at the Zynq end?
12-17-2013 06:18 AM
That sounds like an output standard ("F" meaning fast slew rate). Did you use a generic IBIS model or did you generate it for your design using IBISwriter?
02-07-2014 05:50 AM
Source termination resistor value should be:
Rs = <trace impedance> - <driver output impedance>.
So putting 22..33 Ohm instead of 50 Ohms should do the trick.