04-24-2018 11:32 AM - edited 04-24-2018 11:50 AM
Is there any Xilinx block which can do the job.
 PL based register IP block which can be accessible from Linux.
 once written this value should be applied to next block.
 one of the internally created IP requires switching modes by writing to 4 bit line [3:0].
 I wanted to be able to write from Linux to that axi register and then the register will apply the value b'0101 to custom IP block port.
 I wanted to see if there is a IP from Xilinx which can do the job.
Linux ---AXI protocol--> register [3:0] --> internally created IP's port [3:0].
 i explored AXI-register slice, but it did not fit my purpose, please comment if i am wrong.
 i am ok with DDR based access or OCM based access. dont want to waste too much memory for this. 32/64 bit implementation fits usage.
04-24-2018 11:33 PM
you can create an AXI Peripheral (register map) and then connect the registers of your module to the registers of this peripheral. You can do this by instantiating your logic inside the AXI Peripheral. There is a Xilinx video where the creation of an AXI Peripheral is explained: https://www.xilinx.com/video/hardware/creating-an-axi-peripheral-in-vivado.html
On the Linux side, you will need a kernel driver to access the register. You can write your own one or use a UIO driver. If you don't need an extreme performance, UIO is a good solution because it avoids writing some kernel code. If you just have to write some values on the register and manage one interrupt, I would go this way. Maybe you find this blog post useful: http://fpga.org/2013/05/28/how-to-design-and-access-a-memory-mapped-device-part-two/
04-30-2018 07:03 AM
You can just use an AXI GPIO with a UIO:
The above uses a interrupt, which you prob dont need. However, the steps to add the UIO
are usefull. The second wiki has some example code you can use.