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Registered: ‎08-18-2014

Little-endian MicroBlaze register bit numbering

Hi!

I'm a bit confused. If I look at the Microblaze Processor Reference Guide (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug984-vivado-microblaze-ref.pdf), for example the MSR (machine status register), and look at the bit DCE (data cache enable), it is specified as the 24. bit.

However, the assembly code for enabling data cache, does this:

microblaze_enable_dcache.S:

mfs r8, rmsr
ori r8, r8, 0x80
mts rmsr, r8

That 0x80 is the total opposite of what I would write based on the ReferenceGuide: 1<<24 would be 0x1000000.

0x80 is 1<<(31-24), so it seems to me, that the actual bit numbers are as they would be reversed in the 32bit register.

If we have a look at the code for MMU configuration in the Xilkernel, this is the same for the TLBHI/TLBLO register manipulation code as well (mpu.c)

What is the reason for this?

(I'm using MicroBlaze with C_ENDIANNESS: little-endian on Zynq)

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Registered: ‎08-18-2014

Re: Little-endian MicroBlaze register bit numbering

I found this in the reference: "bit-reversed format". Does it mean this? Why would anybody do this? It is very misleading.
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Registered: ‎08-18-2014

Re: Little-endian MicroBlaze register bit numbering

Even the official Xilinx Linux kernel (https://github.com/Xilinx/linux-xlnx/blob/ebfe386588bfbda9b9ad153d4bcd56d452e8c98f/arch/microblaze/include/asm/registers.h) defines these bits like this:
#define MSR_DCE (1<<7) /* 0x080 */
Why can't you put it into the reference like that?
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