04-09-2019 03:04 AM
I'm a bit confused. If I look at the Microblaze Processor Reference Guide (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug984-vivado-microblaze-ref.pdf), for example the MSR (machine status register), and look at the bit DCE (data cache enable), it is specified as the 24. bit.
However, the assembly code for enabling data cache, does this:
mfs r8, rmsr
ori r8, r8, 0x80
mts rmsr, r8
That 0x80 is the total opposite of what I would write based on the ReferenceGuide: 1<<24 would be 0x1000000.
0x80 is 1<<(31-24), so it seems to me, that the actual bit numbers are as they would be reversed in the 32bit register.
If we have a look at the code for MMU configuration in the Xilkernel, this is the same for the TLBHI/TLBLO register manipulation code as well (mpu.c)
What is the reason for this?
(I'm using MicroBlaze with C_ENDIANNESS: little-endian on Zynq)
04-09-2019 06:07 AM
04-10-2019 01:32 AM