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Registered: ‎05-19-2017

Lock Zynq PS Data Address Offsets and ranges.



We have a Zynq based design and we are hoping to lock the Offset Address and Range of all the IP's on our design. The goal of locking this addresses is to avoid recompiling software and avoid potential problems if addresses are not correct.

I was trying to accomplish this by creating a pre-synthesis tcl command. Doing so would set up the addresses in that tcl command every time we do a synthesis. Then we just need to take care of that tcl file with the addresses to make sure the offsets will always be the same.


My idea was to do something like this:

namespace eval _tcl {
  proc get_script_folder {} {
     set script_path [file normalize [info script]]
     set script_folder [file dirname $script_path]
     return $script_folder
variable script_folder
set script_folder [_tcl::get_script_folder]

open_project $script_folder/project/project.xpr
open_bd_design $script_folder/project/project.srcs/sources_1/bd/design/
#Modify address segments
set_property offset 0x43C60000 [get_bd_addr_segs {processing_system7_0/Data/SEG_1_Reg}]  
set_property offset 0x43C50000 [get_bd_addr_segs {processing_system7_0/Data/SEG_2_Reg}]
set_property offset 0x43C00000 [get_bd_addr_segs {processing_system7_0/Data/SEG_3_Reg}]
set_property offset 0x43C10000 [get_bd_addr_segs {processing_system7_0/Data/SEG_4_Reg}]
set_property offset 0x43C40000 [get_bd_addr_segs {processing_system7_0/Data/SEG_5_Reg}]
set_property offset 0x43C70000 [get_bd_addr_segs {processing_system7_0/Data/SEG_6_Reg}]

close_bd_design [current_bd_design]

The tool is not very happy with this. The problem I see is that the pre-synthesis tcl command doesn't really run pre-synthesis. If the tool would source the presynthesis.tcl command and wait it to finish and then start the synthesis my idea would work (Probably).


Is there any way to lock the offset addresses? I recall there was a version of Vivado where there was a checkbox to lock the offsets. I am working with Vivado 2017.1

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