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chandan_e
Observer
Observer
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Registered: ‎11-06-2013

LogiCORE IP System Cache Statistics

Hi,

 

I'm using the System Core IP v3.0 in a Zynq Vivado design. I'm using only the generic port of the IP and I'm able to read the statistics counters. However I'm not sure how to interpret them. For example, under "Statistics and Control" in chapter 1 of the User's Guide, it says that there are counters for read and write transactions. But in Table 2-13, I see only "Read/Write Segments". What do these mean?

 

Also, what are "Locked Read/Write Hit"? And First Write Hit?

 

How do I interpret Read/Write Latency? Are these cumulative across all Read/Write transactions?

 

If someone can point me to a more detailed description of these counters, I would be very grateful.

 

Chandan

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rikardw
Visitor
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Registered: ‎07-18-2016

Hi Chandan,

 

These are the counters you are looking for. For Optimized ports it is a 1:1 mapping between transaction and segment. Generic ports there can be multiple segments for a transaction since arbitrary AXI4 transaction settings are supported, for example when a transaction span multiple cache lines.

 

First Write Hit is counted in the transition from Clean -> Dirty, i.e. only the first write to a cache line.
Write Hit is counted every time a write has a Hit on a cache line.

 

Locked Read/Write Hit is when a hazard has been detected that need special handling to guarantee data integrity. This is automatically handled by System Cache but this special handling to resolve the conflict/hazard will add extra latency compared to a regular Hit.

 

All latency counters (Table 2-10, 2-11 and 2-16) are defined as having the counter data type described in Table 2-18 (and 2-23). This data type contain number of events, sum of x, sum of x^2, min, max and flags. With this data all regular statistic information is available directly or can be calculated from the data provided, such as mean etc.
Each of these latency counter has an associate configuration register (Table 2-25 and 2-26 for read and write respectively) that define start and stop events for the latency measurement.

 

All table references are from pg118, System Cache v3.1

 

Regards,
Rikard

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