Low Latency transfer of small data chunk PL->PS via AXI GP

[orangelynx]

Hi everyone,

I have a ZC706 evalboard and I'm trying to get started with PL-PS communication. I want to be able to transfer small chunks of data (4 bytes) from the PL to the PS and make the PS process them ASAP. Some FIFO would be nice at later stages as well.

For some reason, the CDMA example in UG1165 (zynq embedded development tutorial) didn't quite work for me (I started a clean project but it won't let me map HP0_DDR_LOWOCM to 0x2000_000 - "This peripheral is limited to a fixed base Address of 0x00000000[ 1G ]..." etc. and I don't seem to be able to resolve this error.

Either way, for the main goal I actually wanted to use the AXI GP interface, because I think that it suffices for my purpose. I'm just not sure where I should map the memory to (DDR isn't possible, correct?). So BRAM seems to be my ticket?

Any help would be appreciated.

[drjohnsmith]

Ifyou use the AXI ports, 

then your going to have a fifo on the ARM side, no matter what you do.

fastest I think is to get the PL to post in PS memory the 4 bytes, then interupt the PS to grab the data.

If you have to hand shake or such like, then its going to be high latency.

    In my view, The ARM bus is designed for High throughput, not low latecy,

Look at all the examples of Zynq, they are for video streaming and such like, not real time.

so far I've ended up using picoblaze and the microblaze in the PL as they are faster at handeling the data / interupt. 

[muzaffer · Accepted solution]

What is low latency for you? You can create a slave IP block, connect it to a GP port and have the processor read the data. With this setup, you can read/write 4 bytes roughly in 150ns or so. You can make your slave IP generate an interrupt which has its own latency.

[drjohnsmith]

good point , whatis low latency ?

with the Dual ARMs running at say 1 ns clock cycles, 150 ns is a long time, especialy if you have to wait the ARMs while you get the answer.

Its an inherent feature of using high speed decoupled processors, not much anyone can do if you want to use a high speed  processor as opposed to say a DSP or Micro Blaze.

[orangelynx]

Sorry for the late response

I'm just looking for the best latency-minimizing approach to implement a PL-PS Datalink. muzaffars approach seems good enough to me, thanks.