Hi, I am in need of a fast low latency interface between PS - PL. I have read the TRM and similar documents and figured out that AXI4 (128-bit) FPD is probably the best interface for me.
However, in the PL logic, my data is just a block of ~ 1800 bits. I have to provide read/write access to it from PS.
Is BRAM/URAM the best alternative for me? Can I load BRAM on every clock cycle with 1800 bits in PL?
Device: Zynq MPSOC (19EG).