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Newbie
Newbie
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Registered: ‎09-28-2020

M_AXI_GP clock domains

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Hi there,

I want to clarify something about figure 5-1 from UG585.

I notice there is an ASYNC block between M0 and M1 and S0 and S1 of the general purpose AXI ports. Does this imply that there is some sort of clock-domain crossing implemented by default? Suppose I were to connect an AXI slave peripheral directly to one of these master ports, but clocked off of a separate clock on the PL. Would I need to implement an AXI Clock Converter, or is there one already in the PS?

 

Thanks

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Moderator
Moderator
218 Views
Registered: ‎11-09-2015

HI @gisellegk 

Yes there are CDC logic for all the AXI interfaces between the PL and PS as mentioned in the page 128:

trm.PNG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
219 Views
Registered: ‎11-09-2015

HI @gisellegk 

Yes there are CDC logic for all the AXI interfaces between the PL and PS as mentioned in the page 128:

trm.PNG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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