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Scholar
Scholar
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Registered: ‎08-24-2011

MDIO interface between the PS and PCS/PMA connects incorrectly via hierarchy boundary

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I develop a firmware for the UltraScale+ SoC with multiple Ethernets connected via SFP.

Unfortunately, the block diagram was quite complicated. Below is the version simplified to a single Ethernet:

 

design_OK.png

 

To allow the end-user to easily copy the Ethernet block to his full design, I have moved the Ethernet interfaces with the surrounding infrastructure to the hierarchical sub-block. Below is again the simplified version:

design_BAD.png

It appeared, however, that the block copied to the final design does not work correctly. The PCS/PMA PHY was not recognized.

I have checked my hierarchical design, and it was working correctly, but when I removed the connection between the MDIO_ENET0 port in the PS and the mdio_pcs_pma port in the ether sub-block, the same problem happened.

I have investigated implemented designs, and have found that the MDIO interface is connected correctly in the first design:

 

signals_OK.png

 

But not in the last one:

 

signals_BAD.png

 

Of course the same problem occured, when the end-user has connected the ports of the copied block in his full design.

It seems, that the Block Designer does not connect correctly the MDIO interfaces through the hierarchy boundaries.

Probably it is somehow associated with the definition of the "xilinx.com:interface:mdio_rtl:1.0" interface.

 

I attach the sources of the affected design.

 

Regards,

Wojtek

 

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Scholar
Scholar
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Registered: ‎08-24-2011

Re: MDIO interface between the PS and PCS/PMA connects incorrectly via hierarchy boundary

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I have recreated the project in 2017.4 from the scratch and repeated the whole procedure.

It seems, that now the interfaces are connected correctly. So probably the problem was fixed somewhere between 2016.4 and 2017.4

I attached the project recreated in 2017.4.

Regards,

Wojtek

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Scholar
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Registered: ‎08-24-2011

Re: MDIO interface between the PS and PCS/PMA connects incorrectly via hierarchy boundary

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The problem still exists in Vivado 2017.4

 

With best regards,

Wojtek

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Registered: ‎08-25-2009

Re: MDIO interface between the PS and PCS/PMA connects incorrectly via hierarchy boundary

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Hi @wzab, Do you mean the MDIO interface has been driven to 0 in some versions of Vivado? What version was working for you, and what versions are not?

 

We have Xilinx reference designs XAPP1305 and XAPP1306 which are also using similar setup and there isn't an issue there. Have you taken a look at those already?

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Scholar
Scholar
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Registered: ‎08-24-2011

Re: MDIO interface between the PS and PCS/PMA connects incorrectly via hierarchy boundary

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The problem occurs only when the MDIO connection is done between blocks located on different levels of BD hierarchy (as I have shown in the first post in the thread).

The XAPP1305 does not use nested hierarchy in the BD design (see the Figure below)

Zrzut ekranu z 2018-03-02 21-46-10.png

That's why the problem does not occur in XAPP1305, and occurs in my design.

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Scholar
Scholar
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Registered: ‎08-24-2011

Re: MDIO interface between the PS and PCS/PMA connects incorrectly via hierarchy boundary

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I have recreated the project in 2017.4 from the scratch and repeated the whole procedure.

It seems, that now the interfaces are connected correctly. So probably the problem was fixed somewhere between 2016.4 and 2017.4

I attached the project recreated in 2017.4.

Regards,

Wojtek

View solution in original post

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