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Observer
Observer
9,015 Views
Registered: ‎12-05-2008

MIG/MPMC

Hi there 

 

I'm a little confused about the relation between MIG and MPMC.

 

If I create a microblaze design with an MPMC core on my PLB do I still need to use MIG to create an SDRAM controller or does EDK handle that implicitly?

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13 Replies
Highlighted
8,996 Views
Registered: ‎08-21-2008

Hello.

Actually the real relationship b\w MIG and MPMC will come into picture when you move further from SDR SDRAM towards DDR or DDR2.

For DDR or DDR2 passing the UCF through MIG is very important and the whole banking selection for DDR has to be done according to the generated UCF through MIG.

We also use the constraints in our UCF file generated in the UCF file of MIG. 

Best of luck.
--
Unlimited in my Limits.
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Observer
Observer
8,977 Views
Registered: ‎12-05-2008

Thanks for the reply.  It is DDRII sdram which I am using.  

 

I'm a confused though I allready have UCF files for my board which were suppllied by the manufacturer.  Will these still need to be run through MIG?  What exactly does MIG do to the UCF?   

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Highlighted
8,969 Views
Registered: ‎08-21-2008

Hello.

See, the UCF file provided to you by the manufacturer must be in accordance with the UCF file generated by MIG.

You can try one option at your end.

MIG also has the facility of taking the user made UCF and validating it whether it will work or not.

Try to give your UCF to MIG and see if it passes that or not.

Also on the coding part were you able to generate the bitstream without any errors with the provided UCF.

By the way which version and service pack are you using.

 

MIG assigns proper banks to different address, data and control lines. Also it generates constraints vital for your DDR2 controller to run inside FPGA flawlessly. 

That is why the routing of the PCB for DDR2 should match the various banks assigned by the MIG. 

Best of luck.
--
Unlimited in my Limits.
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Observer
Observer
8,967 Views
Registered: ‎12-05-2008

Ok I'm starting now to understand the design flow.  I spent all day on this.

 

This is what I have done.

 

1.  Using MIG I create a design for a memory controller.  I specify the details of my ddr2 sdram.  At this point I specify the banks which should be used for the memory interface pins in the ucf file.  Mig then creates a UCF file which has the connections in the correct banks but not the correct pins.

2.  I alter the UCF file to have the correct pin locations and then verify this using MIG.

3.  I now use the perl script convert_ucf.pl to create an MPMC ucf file from my MIG ucf file.  This changes the names of the pins to match my MPMC core.  (I've now changed both the names of the constraints and the loc values, this seems strange.  How are my new constraints related to the other rules generated by mig?)

 

Now when I try to generate a bitfile I get some errors like the following 

 

ERROR:Place:292 - The components

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[1].u_iob_dq/stg3b_out_fall and

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[0].u_iob_dq/stg3b_out_fall seem to be placed / locked to the same site

   SLICE_X0Y159

ERROR:Place:292 - The components

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[1].u_iob_dq/stg3b_out_fall and

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[0].u_iob_dq/stg3b_out_fall seem to be placed / locked to the same site

   SLICE_X0Y159

ERROR:Place:292 - The components

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[1].u_iob_dq/stg3b_out_fall and

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[0].u_iob_dq/stg3b_out_fall seem to be placed / locked to the same site

   SLICE_X0Y159

 

There are many more but they all say the same thing only for different values of gen_dq.  It seems to me these errors are caused because of the following constraints genereated by MIG

 

 INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y159;

INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y159;

INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y158;

INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y158;

 

0 and 1 both allocated to X0Y159

 

I'm trying the whole process now from scratch to see if I can find the point where things go wrong. 

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Observer
Observer
8,962 Views
Registered: ‎12-05-2008

I should add that I'm using 10.1.03 EDK/ISE  I'm using MIG 2.3 with MPMC4.

 

The UCF file supplied with my board only has pin locs so I'm guessing it's not going to do the job.  

 

My board is designed to be compatible with MIG though. 

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Xilinx Employee
Xilinx Employee
8,942 Views
Registered: ‎10-23-2007

After step 2 where you verify the design with MIG, can you run the MIG design and UCF through the tools (before the perl script)?  Does it pass successfully?
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Highlighted
8,940 Views
Registered: ‎08-21-2008

Hello.

If you are using 10.1.03 then you don't have to run the perl script. You just have to match the names. 

Have you tried passing your UCF through MIG for DDR2.

Does it pass?? 

Message Edited by prateek_bhatt on 09-15-2009 09:33 PM
Best of luck.
--
Unlimited in my Limits.
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Observer
Observer
8,929 Views
Registered: ‎12-05-2008

Thanks for the replies.  I wasn't sure what the point of the perl script actually was so I'll leave it out of my flow for the moment.

 

If I simply create the mig project with my DDRII details and then alter the UCF to have the correct pin locs then run it through verify with MIG I get no errors but I do get some warnings 

 

/*******************************************************/

 

/* Controller 0

/*******************************************************/

Checking pins allocated to Data bits ...

Checking pins allocated to Strobe bits ...

Checking pins allocated to Mask bits ...

Checking pins allocated to Clock bits ...

Checking pins allocated to Control bits ...

Checking pins allocated to Control bits ...

Checking pins allocated to user_interface bits ...

Checking pins allocated to user_interface bits ...

Checking pins allocated to user_interface bits ...

Checking pins allocated to Control bits ...

Checking pins allocated to Address bits ...

Checking pins allocated to BankAddress bits ...

WARNING : Signal ddr2_cs_n[1] expected, but not present in the UCF.

WARNING : Signal ddr2_odt[1] expected, but not present in the UCF.

WARNING : Signal sys_clk_p expected, but not present in the UCF.

WARNING : Signal sys_clk_n expected, but not present in the UCF.

WARNING : Signal clk200_p expected, but not present in the UCF.

WARNING : Signal clk200_n expected, but not present in the UCF.

WARNING : Signal sys_rst_n expected, but not present in the UCF.

WARNING : Signal phy_init_done expected, but not present in the UCF.

Verification completed.

All signals in the UCF were allocated correctly.The number of pins missed in the selected ucf are 8.

 

The cs_n and odt warnings are because I only have 1 of each on my board.  I can change this in the generic parameters here /user_design/rtl/ddr2_sdram.vhd but that doesn't seem to update the MIG project file.  

 sys_clk, clk200 and sys_rst will all be provided internally so they won't need to be in the ucf file and phy)init_done I'm guessing is another internal signal.

 

So far so good?  

 

I'm now going to create a simple embedded design with a ublaze connected to an MPMC and swap in this new UCF file.

 

 

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Highlighted
8,915 Views
Registered: ‎08-21-2008

hello.

The warnings are OK because you may not be using them but see to it that you don't lose any important signal.

Also phy_init_done pin is a very imp signal as it tells whether the calibration was successful or not.

After calibration only you can write and read DDR2.

Map the signal above to some LED on-board.

The LED should glow after you download your code in FPGA. 

Best of luck.
--
Unlimited in my Limits.
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Participant
Participant
4,253 Views
Registered: ‎08-25-2008

Hi rvabdn,

 

I've got the same error that you're (were) showing, even down to the slice (SLICE_X0Y159).

 

ERROR:Place:292 - The components

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[1].u_iob_dq/stg3b_out_fall and

   ddr2sdram/ddr2sdram/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/gen_

   dq[0].u_iob_dq/stg3b_out_fall seem to be placed / locked to the same site

   SLICE_X0Y159

 

It looks like your posting is from almost a year ago... you wouldn't happen to remember how you solved it would you?

 

Thanks,

Randy

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Observer
Observer
4,244 Views
Registered: ‎12-05-2008

My only suggestion is to get rid of those rules all together.

 

I got a working example from the manufacturer of my board and it doesn't have any routing constraints.  All it has in the UCF is pin allocations and clock constraints and it works 100%.

 

I still don't fully understand the point of MIG. 

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Participant
Participant
4,242 Views
Registered: ‎08-25-2008

I fixed it. 

 

I wasn't setting the C_MEM_DQS_IO_COL and C_MEM_DQ_IO_MS values correctly in the .mhs file. 

 

Specifically, the MPMC IP Config GUI wrote default values to the .mhs for C_MEM_DQS_IO_COL and C_MEM_DQ_IO_MS of the form 0x00000000 (hex)  rather than 0b000000000 (binary) as they are in the .vhd file from MIG (they're bit_vectors).  Had to change the 'x' to a 'b' in the .mhs to recognize the binary representation from MIG and all was well.

 

do

 

 PARAMETER C_MEM_DQS_IO_COL = 0b0000000000000000
 PARAMETER C_MEM_DQ_IO_MS = 0b1010010110100101101001011010010110100101101001011010010110100101

 

not

 

 PARAMETER C_MEM_DQS_IO_COL = 0x0000000000000000
 PARAMETER C_MEM_DQ_IO_MS = 0x1010010110100101101001011010010110100101101001011010010110100101

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Visitor
Visitor
3,288 Views
Registered: ‎05-28-2008

Thank you! I encountered the same problem.

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