08-28-2014 06:34 AM
Can anyone point me to documentation that describes the state of the MIO Banks during VCCO_MIO Ramp Up?
I'm seeing them follow VCCO_MIO as it ramps.
I specifically need one of the MIO pins to be held low or tristated during VCCO_MIO Ramp Up (if thats even possible), otherwise it resets my power circuit.
Is there a way to control this or do I need to implement some external circuitry?
Would moving this connection to logic be a better choice?
08-28-2014 07:52 AM - edited 08-28-2014 08:01 AM
The FPGA IOB IO pins are designed to be tristate until the configuration is loaded. (with a weak pull up, or pull down enabled if set) prior to DONE going high.
The processor system IO (MIO) is ARM designed, and has no conditions defined prior to their configuration that I am aware of. (but see below -- in ds187 next post)
If you require a guaranteed state prior to DONE being asserted, I suggest you use the programmable logic IO pins, instead.
If I am wrong, I am sure I will be corrected.
Am I wrong? Anyone? Did we open up the ARM IP and verify its before configured state?
(I have corrected this myself -- they are tristate before they are programmed)
08-28-2014 08:00 AM - edited 08-28-2014 08:02 AM
ds187 does state the PS IO's are tristate on power on....
If its in the datasheet, then I am going to assume it to be correct (and my first answer is in error),
08-28-2014 09:08 AM
The recommended power-on sequence is VCCPINT, VCCPAUX, and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.
My supplies boot in the following sequence:
2. VCCPAUX and VCCPLL
3. VCCO_MIO0, VCCO_MIO1, and VCCO_DDR
I'm not seeing the MIO pins tristate. They immediately rise to 3.3V and stay there, even though I've pulled it low.
Could my power supply boot sequence explain why I'm not seeing them tristate?
I chose this sequence to accomodate the PL recommended power on sequence.
08-28-2014 09:12 AM - edited 08-28-2014 09:14 AM
I do not know, but when the data sheet states something true for one sequence it is unsafe to assume it is also true for another sequence.
Perhaps someone else may comment?
I know how the FPGA IOB's initialize, and why they require their sequence, but I am unfamiliar with the PS IO's.
Further, the IO's all have diodes to their Vcco, and to ground, so it is sometimes difficult to "see" what is happening. I use a 3.3K to a separate 3.3v supply, and another 3.3K to ground (voltage divider) connected to the IO pins to be able to see exactly what is happening, pull up, pull down, diode forward conducting, tristate, etc.).
01-12-2015 01:08 PM
Has anyone received any definitive answer on this subject? I have a new design in which we need to know the state of the PS_MIO pins the instant after power ramp-up of VCCO_MIO0/VCCO_MIO1 has occurred, but before the PS begins executing the BootROM code in the on-chip ROM.
I would like to avoid having to make a prototype, using your handy dandy 3.3K voltage divider circuit just to try and see what is exactly happening on every single MIO pin at this stage of power-up.
The closest Answer Records I could find related to this are:
AR# 56787 (http://www.xilinx.com/support/answers/56787.html)
This discusses the state of MIO pins when holding PS_POR_B low, but this would probably be a fair amount of time after power-up.
AR# 47573 (http://www.xilinx.com/support/answers/47573.html)
Addresses the behavior that the BootROM imposes on the MIO pins via an .INT file linked into the Boot image using BootGen, but tells us nothing of the MIO before the BootROM is alive and kicking.
01-12-2015 01:13 PM
As no one commented, I will ask the team that designed it, and post back.
After reading the AR's, I suspefct that the state before the boot rom executes is ANY (high, low, tristate).
They seem to go out of their way to define the state after boot.
01-13-2015 08:22 AM
The best answer I can get is:
The TRM (UG585) described PIN STATE for boot, reset, etc.
Not all pins are tristate in all tables. (!!!)
Use "find" to search for "pins state" and look at your boot mode (that table which describes your mode to boot).
01-13-2015 09:02 AM
the correct answer is
the pin state listed in UG585 apply when BOOTROM has executed init code, if not they are ALL tristate with weak pullup.
the only process that can change the pin state is CPU0 executing bootrom code, hence if POR_B is held low, CPU0 is not EXECUTING then the pins are all tristate.
01-13-2015 05:15 PM
An older (2012) Zynq design of mine had the requirement that a paricular MIO pin be low during power supply ramp up.
I was using an IO supply voltage of 1.8V and the core (1.0V) was stable before the 1.8V rail started to ramp.
I used a fairly strong pulldown (120ohm, IIRC) on the MIO signal.
During testing I didn't see any glitch on the signal during power up.
Possibly I couldn've used a weaker pulldown, but I didn't try that.
01-13-2015 05:36 PM
I should clarify - the downstream device that was being driven by that MIO output had a switching threshold of about 0.4V.
We've made multiple batches of that product, and no failures have ever been seen, which means that the MIO output never rose above 0.4V during startup, even across a (presumably wide) production spread.