11-13-2015 10:55 AM
I'm trying to bring up a new board using a Micrel KSZ9031 ethernet PHY connected via MIO to my Zynq.
I configured MIO6 to be ENET0 reset (LVCMOS 1.8V, slow, pullup disabled (cannot be changed), out, Active LOW).
Now independent of whether I select 'Active High, or Active Low' the generated ps7_init_gpl files look *exactly* the same?!
The generated .xci file changes depending on the setting.
I hooked up a scope and I cannot see the pin wiggle either, so I'm starting to wonder if there's something wrong.
Is my assumption that the FSBL should toggle the reset and leave it either high, or low depending on the 'Active high/low' setting wrong?
11-15-2015 12:47 PM
11-15-2015 06:43 PM
I don't see either the macb or the xilinx_emacps driver using the gpio property. Am I missing something here?
Would it be up to the phy driver? Is there some devicetree magic I'm not getting?
11-15-2015 11:39 PM
11-16-2015 12:59 PM
I did a git grep on both mainline and xilnix tree, the string 'enet-reset' or 'xlnx,enet-reset' doesn't show up. If *anything* picks it up from the dts I'd expect it to show up. Any other ideas?
09-12-2016 04:00 AM - edited 09-12-2016 04:49 AM
I can only confirm that with petalinux 2016.2 this is still the same. The generated code does not change whether the reset is configured active-low or active-high. Not for the FSBL and not for the device-tree.
I do see some wiggling of the reset line which is correct for an active-low reset.
09-12-2016 06:29 PM
09-27-2016 01:27 PM
In my case the FSBL does generate the reset (without any manual interventions on the generated code). But it is always for an active-low reset. And u-boot or linux have no knowledge of the reset and thus do not generate it.